Fermi texture cache Does Fermi have a texture cache?

Does Fermi have a texture cache or are texture reads simply reads from L2 that bypass L1?
Is ECC lost when doing texture reads?
No speculative answers, please.

Yes, Fermi has a texture cache. Just read the manual to confirm - look at the table in appendix G where it lists a “Cache working set per multiprocessor for texture memory” for all compute capabilities.

On ECC in the tex cache: From the Fermi whitepaper: “Fermi’s register files, shared memories, L1 caches, L2 cache, and DRAM memory are ECC protected …”. You asked for no speculation, so I will give none. I doubt you’ll get a more definitive answer than this unless you are either lucky and an NVIDIA rep responds, or some very smart person writes a microbenchmark that can tell if the tex cache has ECC or not.

I have a definite confirmation.
Correct, Fermi has texture caches, 12 KB L1 per SM.
There is also another level (call it L1.5).
Fermi’s texture caches are not ECC protected, but due to their small size, they are not expected to hold data for too long.
Data mostly streams through them, so problems are not expected in any but the largest machines.