FIQ Interrupt Latency Test with tegra2


My first step was simple. I just implemented a GPIO, which triggers a IRQ in a Linux Kernel Module (LKM). Now I am trying to implement a GPIO, which triggers a FIQ. The problem ist, that I don’t get in my FIQ Handler.

First I request a GPIO (J6):

gpio_request_one( 78,  GPIOF_IN, DRV_NAME " fiq" );
gpio_J6_IRQ = gpio_to_irq ( 78 );

This works fine, because this is the same code as the IRQ Interrupt Latency test.

Now the FIQ part:

retval = claim_fiq( &FIQ_Latency_Handler );
if ( ... ) { /* Error handling */ }

set_fiq_handler( pFIQHandlerStartAddress, dwFIQHandlerLengthByte );

then I tryed:

enable_fiq( gpio_J6_IRQ );

as well as:

tegra_fiq_enable( gpio_J6_IRQ );

But nothing works. The FIQ Handler is never called.

Best regards,

Hi again,

What I found out is, that I just can enable FIQ for a whole GPIO bank. I tried with:

enable_fiq( INT_GPIO3 );

A unbalanced enable for IRQ 66 occured. When I do first a disable_fiq( INT_GPIO3 ); and after an enable_fiq( INT_GPIO3 ); I do not get this message. But still the FIQ handler seems not to be called.

I tried again with the

tegra_fiq_enable( INT_GPIO3 );

Here it seems that somthing is going on, because when I trigger my GPIO the Linux system blocks somehow. But I don’t know exactly what is going on.

Has anyone used FIQ with Tegra2? It doesn’t matter with GPIO, Timer, or whatever.

Best regards,

Hi again,

It seems that the FIQ Handler is called. I get a message:

Bad mode in data abort handler detected
Internal error: Oops - bad mode: 0 [#1] PREEMPT SMP
Modules linked in: FIQLatency

PC is at 0xffff001c
LR is at ns_to_timeval+0x30/0x48

Flags: nzCv IRQs off FIQs off Mode FIQ_32 ISA ARM Segment kernel

It looks like that it crash at the assembly line to clear the interrupt bit.

STR r8, [r9]

Here a snip of code from my LKM init function:

#define GPIO3_BASE_ADDRESS 0x6000D104
#define GPIO_CLR 0x70


// pGPIO3Base is 0xfe20d104

// GPIO J5 Clear Bit
regs.ARM_r8 = 0x20;

 // GPIO 3 Base Address
regs.ARM_r9 = (long)pGPIO3Base + GPIO_CLR;
set_fiq_regs( &regs );

Hope anybody can help me this time :).

Thank you very much.

What is your end goal?

I don’t know anything about the FIQ interrupts but I’ve understood they are really limited in what they can do.

Hi kulve,

As first I just would like to implement a FIQ Latency test. So just toggle a GPIO output. If the maximum latency time will be lower then 100 us I would like to copy some data over the GMI with dma.

Best regards,


Why can I not access inside my FIQ Handler the GPIO Register (Mode FIQ_32)?

I tried with the macro

// pGPIOJBase is 0xfe20d104
// pGPIOJBase is 0xfe20d104
pGPIOJBase = ioremap( GPIO3_J_BASE_ADDRESS, 0x100 );

Assembley code:

STR r8, [r9]

What is the problem with this address access?



I do not always get a data abort handler detected message. When I don’t get it then my FIQ Handler is working. Somehow it is also working, when I get a data abort handler detected message.

So first question why do I get a:

Bad mode in data abort handler detected

When it is working it seems that it comes twice or more often into the FIQ handler for one interrupt.

The first image is when it is working fine

The second image is when it is working wrong

Assembly FIQ Handler code (Maybe the code is not anymore compatible with the source code above):

  • J5 Input
  • J6 Output

	// Register r10 GPIO3 J CLR Register address
	MOV	r11, #0x20
	STR	r11, [r10]

	// Register r9 GPIO J Output Register address
	MOV	r8, #0x40
	LDR	r11, [r9]

	// Toggle Flag
	EORS	r11, r8
	STR	r11, [r9]

	subs	pc, lr, #4			// return from FIQ