Hi,
I use Jetson thor and a custom borad, SDK version r38.2
I’m going to config UPHY as PCIe :C1x1+C2x2+C3x2+C5x4 +MGBEx4
serial.log (128.6 KB)
uphy.diff.txt (1.4 KB)
pcie.diff.txt (886 Bytes)
Flash failed after I updated the bpmp.dtb
Hi lzyu1110,
Have you referred to the following guide for UPHY configuration?
Jetson Thor Adaptation and Bring-Up — NVIDIA Jetson Linux Developer Guide
Do you mean that the flash is successful before updating bpmp-dtb?
Please also share the full flash log for further check.
so, how can I enable PCIE C3?
any updates?
This error occurs as long as I config uphy1-config as <0x8>.
Are you sure the dtb got flashed to the board really has C4 disabled?
kernel_tegra264-p4071-0000+p3834-0008-nv.dts.txt (325.1 KB)
This file is the result of decompiling /boot/dtb/kernel_tegra264-p4071-0000+p3834-0008-nv.dtb.
I added this file to /boot/extlinux/extlinux.conf
FDT /boot/dtb/kernel_tegra264-p4071-0000+p3834-0008-nv.dtb
I can find PCIe C4 node has been disabled.
pcie@a808460000{ status = “disabled”… }
please do full flash instead of only updating FDT in extlinux.
PCIe C4 in BSP is disabled default in BSP.
I’ve done full flash before (setting uphy1-config to 7).
How did you flash your board?
I don’t think the change you are doing for C4 and C5 are needed.
C4 is by default disabled as you said, then why are you still setting it again to “disabled” in your DT?
Could you also disable MGBE in the DT first to see if that could bypass the error?
flash
sudo ./l4t_initrd_flash.sh jetson-agx-thor-devkit internal
I need to use 2 MGBE and MGBE now works bad.
21.284828] nvethernet a808e10000.ethernet: [sw_ovveride_method_for_uphy_rx_lane][705][type:0x4][loga-0x80000102] RX_CAL_EN polling timeout:
[ 21.284859] nvethernet a808e10000.ethernet: [xpcs_lane_bring_up][813][type:0x4][loga-0x0] UPHY Rx lane bringup failed with sw ovveride method
[ 22.116988] nvethernet a808a10000.ethernet: [sw_ovveride_method_for_uphy_rx_lane][705][type:0x4][loga-0x80000102] RX_CAL_EN polling timeout:
[ 22.117021] nvethernet a808a10000.ethernet: [xpcs_lane_bring_up][813][type:0x4][loga-0x0] UPHY Rx lane bringup failed with sw ovveride method
[ 22.148832] nvethernet a808b10000.ethernet: [sw_ovveride_method_for_uphy_rx_lane][705][type:0x4][loga-0x80000102] RX_CAL_EN polling timeout:
[ 22.148867] nvethernet a808b10000.ethernet: [xpcs_lane_bring_up][813][type:0x4][loga-0x0] UPHY Rx lane bringup failed with sw ovveride method
[ 22.244719] nvethernet a808d10000.ethernet: [sw_ovveride_method_for_uphy_rx_lane][705][type:0x4][loga-0x80000102] RX_CAL_EN polling timeout:
[ 22.244755] nvethernet a808d10000.ethernet: [xpcs_lane_bring_up][813][type:0x4][loga-0x0] UPHY Rx lane bringup failed with sw ovveride method
By the way, lspci result has only C2 and C5, C1、C3 has not appeered yet.
what does uphy1-config = <0x7> mean?
I enabled it wrongly first
please set uphy1 back to 8 disable your MGBE first. Just for debug.
Not asking you to disable forever.
flash still failed when MGBE is disabled.
please use the demuxer from JetPack7.0_GA/Linux_for_Tegra/tools/demuxer to split the console and dump flash failure log again from bpmp.
It will make garbled info gone to make it readable.
The diff between uphy1 setting of 7 and 8 are just MGBE between 10G and 25G setting.
C5 setting is still same.
So if you want to use 8, change the mgbe speed in your bpmp dt too. 2 to 0x3.
730 mgbe0-speed = <0x02>;
731 mgbe1-speed = <0x02>;
732 mgbe2-speed = <0x02>;
733 mgbe3-speed = <0x02>;
how can I know and control the state of PCIE1_RST_N ?
the result of gpioget gpiochip1 7 is 0.
I can not detect my AX210 wifi module. I opened **hot-plug-capable. **
The output of lspci is
0001:00:00.0 PCI bridge: NVIDIA Corporation Device 22d8
0002:00:00.0 PCI bridge: NVIDIA Corporation Device 22d8
0003:00:00.0 PCI bridge: NVIDIA Corporation Device 22da
Hi,
We just focus on one issue in one topic. For this, we only concern about the flash failure.
If you have any problem with PCIe, please file separate topic.