Hi
I’m trying to get my custom HDMI2CSI adapter board for the Xavier to run and have trouble with the ganged mode. The adapter board is based on the tc358840 chip from Toshiba and works just fine with the TX2. I am using an adapter for the camera connector, therefore the pin assignment should not be a problem.
The HDMI2CSI adapter features 2 HDMI inputs. One input supports 4K and the other just 1080p. Because of the tc358840, the 4K input needs 4 CSI ports and therefore the ganged mode. The 4K input works as intended as long as only a 1080p input is used. As soon as a 4K source gets attached, the vi starts to discarding the frames and indicates that a short line has been received.
[ 2900.507345] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 0, err_data 512
CHANSEL_FAULT channel:0x23 frame:0 vi_tstamp:90993963717 data:0x00000200
I have the following port binding in the device tree:
port@0 {
ret = <0>;
hdmi2csi_tc358840_out0: endpoint {
// csi-port = <0>;
port-index = <0>;
bus-width = <8>;
remote-endpoint = <&hdmi2csi_csi_in0>;
};
};
nvcsi@15a00000 {
num-channels = <2>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
status = "okay";
reg = <0>;
discontinuous_clk = "no";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
status = "okay";
reg = <0>;
hdmi2csi_csi_in0: endpoint@0 {
status = "okay";
// csi-port = <0>;
port-index = <0>;
bus-width = <8>;
remote-endpoint = <&hdmi2csi_tc358840_out0>;
};
};
port@1 {
status = "okay";
reg = <1>;
hdmi2csi_csi_out0: endpoint@1 {
status = "okay";
remote-endpoint = <&hdmi2csi_vi_in0>;
};
};
};
};
vi@15c10000 {
num-channels = <2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
status = "okay";
reg = <0>;
hdmi2csi_vi_in0: endpoint {
status = "okay";
// csi-port = <0>;
port-index =<0>;
bus-width = <8>;
remote-endpoint = <&hdmi2csi_csi_out0>;
};
};
This port binding worked with the TX2. Because the Xavier has the same structure up to port D, I assume that this should still work.
Regarding the signals, I have tested the communication with the tc358840 which works without any problems. Furthermore, I have checked the CSI signal on all ports by probing. The clock for the ports C and D looks good, but only if I’m trying to capture the video the first time after booting. Afterwards, the clock looks odd as there would be some reflections. I guess that’s due to a wrong configuration of the port and is not related to a hardware problem.
In the file csi5_fops.c I found the following function that sets up the CSI ports combined with the lanes. I would expect, that the port 0 (A) and the port 2 (C) are getting activated with four lanes each. That’s also the observation I made on the TX2 within the csi4_fops.c. The port in the csi5_fops.c is hard coded to the index 0 as you can see on line 5. The result is, that the function is called twice setting up the same port. The parameter port_idx is unused, so I tried to use it on line 5 to set up both the port 0 and 2. As a result, the correct ports are used in this function. However, the result stays exactly the same.
static int csi5_start_streaming(struct tegra_csi_channel *chan, int port_idx)
{
int err = 0, num_lanes;
struct tegra_csi_device *csi = chan->csi;
struct tegra_csi_port *port = &chan->ports[0];
u32 csi_pt, st_id, vc_id;
if (chan->pg_mode) {
csi_pt = NVCSI_PORT_UNSPECIFIED;
st_id = port->stream_id;
} else {
csi_pt = port->csi_port;
st_id = csi5_port_to_stream(port->csi_port);
}
vc_id = port->virtual_channel_id;
num_lanes = port->lanes;
dev_dbg(csi->dev, "%s: csi_pt=%u, st_id=%u, vc_id=%u, pg_mode=0x%x\n",
__func__, csi_pt, st_id, vc_id, chan->pg_mode);
if (!chan->pg_mode)
csi5_stream_set_config(chan, st_id, csi_pt, num_lanes);
csi5_stream_open(chan, st_id, csi_pt);
if (chan->pg_mode) {
err = csi5_stream_tpg_start(chan, st_id, vc_id);
if (err)
return err;
}
return err;
}
Do you have any information about how the ganged mode works in the newest release? Is it even supported with the newest version of the CSI and VI?
I am using L4t-r32.2.1. Furthermore I want to mention, that due to the HDMI input no modes are available.