Getting a memory access in ATF

[jongtang.lee]

I’d like to bring up the PCIe device in ATF.

What I’m doing is

1. Add PCIe regions to the MMAP table.
   ++#define TEGRA_PCIERC_BASE U(0x14100000) //plat/nvidia/tegra/include/t194/tegra_def.h
   ++ MAP_REGION_FLAT(TEGRA_PCIERC_BASE, 0x40000U, /* 256KB */
   (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE) //plat/nvidia/tegra/soc/t194/plat_setup.c

• I’ve got the memory address(14100000) from dts.

2. get access to the specific area.
   ++ NOTICE(“debug1 \n”);
   ++ mmio_read_32(TEGRA_PCIERC_BASE + 0x8000U) //plat/nvidia/tegra/soc/t194/plat_setup.c
   ++ NOTICE(“debug2 \n”);

It doesn’t go any further, I mean, never print ‘debug2’.

Am I missing something??
Please give me any advices.

plus, please refer to the below url.

Change atf console log uart

Arm TrustFirmware’s console log is shown on the shared console (ttyUSB3) on Jetpack Xavier AGX devkit. I want to redirect it to other uart. (e.g., /dev/ttyUSB0, /dev/ttyUSB1 or any other) I tried with ENABLE_CONSOLE_SPE as 0 in platform_t194.mk but I can’t see atf console log in any ttyUSBx. What shall I do?

One of my coworker created other topics but same issues.

Thank you.

[vidyas]

Could you please give more context as to why you want to enable PCIe in the ATF?

[jongtang.lee]

I want to enable PCIe in the ATF to try some tests.
Let me know you one example of tests.

1. Configure the PCIe register and then see what happens
   As you know I failed to read values of the register.

I am referring to the L4T R32.5 BSP and CBoot source code to implement them in the ATF.
https://developer.nvidia.com/embedded/linux-tegra

[vidyas]

Honestly, we have not tried this flow.
In the case of the kernel, the Linux kernel’s generic power domain framework would un-powergate the PCIe power partition before the PCIe platform driver’s probe is called. Are you un-powergating the PCIe partition in your code? If yes, please do so. You can look around for examples of un-powergating APIs usage by talking to BPMP-FW.

[jongtang.lee]

We’ve implemented a unpowerate function as you said.
Plus, we added couple of other functions referring to the cboot code.

1. power gating
2. clk disable
3. reset core assert
4. reset apb assert
5. clk enable
6. reset apb deassert
7. enable uphy
8. reset common apb deassert

Unfortunately, the issue is not resolved yet.
We are looking for other ways.

Please let me know if there is a good way

[jongtang.lee]

Could you tell me which devices (e.g., i2c, etc) should be set up prior to bring up the pcie host in ATF BL31?

[vidyas]

In the above sequence, I expect ‘power ungating’ to happen between steps 4 and 5.
Also, after power ungating the respective partition, please follow the Linux kernel driver’s flow and you should be able to get the PCIe link-up.

[jongtang.lee]

Hello,
I found the pcie programming guidelines chapter in Xavier TRM DP09253002.
How can I get the register information about
such as CLK_RST_CONTROLLER_RST_DEV_UPHY_0[SWR_UPHY_RST] or
CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0[SWR_PEX_USB_UPHY_RST] which are refered in the document.