Global Memory access pattern in doc

Accelerated Computing CUDA CUDA Programming and Performance
#1

In ProgrammingGuide_3.0 G 3.2.2

G.3.2.2 Devices of Compute Capability 1.2 and 1.3

…

More precisely, the following protocol is used to determine the memory transactions

necessary to service all threads in a half-warp:

Find the memory segment that contains the address requested by the lowest

numbered active thread. The segment size depends on the size of the words

accessed by the threads:

    32 bytes for 1-byte words,

    64 bytes for 2-byte words,

    128 bytes for 4-, 8- and 16-byte words.

I think it should be warp,not half-warp.so is it right?

#2

In ProgrammingGuide_3.0 G 3.2.2

G.3.2.2 Devices of Compute Capability 1.2 and 1.3

…

More precisely, the following protocol is used to determine the memory transactions

necessary to service all threads in a half-warp:

Find the memory segment that contains the address requested by the lowest

numbered active thread. The segment size depends on the size of the words

accessed by the threads:

    32 bytes for 1-byte words,

    64 bytes for 2-byte words,

    128 bytes for 4-, 8- and 16-byte words.

I think it should be warp,not half-warp.so is it right?

#3

The text is correct - memory (smem and gmem) addresses are processed per half-warp prior to compute capability 2.0.

#4

The text is correct - memory (smem and gmem) addresses are processed per half-warp prior to compute capability 2.0.