# GPIO control on Xavier nx with register writes **URL:** \ **Category:** Jetson Xavier NX\ **Tags:** spi, gpio, kernel\ **Created:** [August 19, 2021, 1:20pm UTC](https://forums.developer.nvidia.com/t/gpio-control-on-xavier-nx-with-register-writes/187050 "2021-08-19T13:20:42Z")\ **Posts on this page:** 10\ **Page:** 1
**Author:** ![msd11](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@msd11](https://forums.developer.nvidia.com/u/msd11)\ **Post date:** [August 19, 2021, 1:20pm UTC](https://forums.developer.nvidia.com/t/gpio-control-on-xavier-nx-with-register-writes/187050/1 "2021-08-19T13:20:42Z")
**Device: Xavier Nx** To toggle GPIO pins, the basic approach is to write 1 or 0 to the “/sys/class/gpio/gpioxxx/value” file. Above approach is fine but being a file operation it is quite slow and not appropriate for very fast operations. I guess we can also do some _ **register level operations to toggle the GPIO** _ and that will be a much faster approach. Could someone please suggest what needs to be done to control GPIO output with register writes ? I was able to refer to some discussions on doing the same task on Jetson Nano but it looks like Xavier needs some other approach. ---
**Author:** ![JerryChang](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/jerrychang/32/14043_2.png) [@JerryChang](https://forums.developer.nvidia.com/u/JerryChang)\ **Post date:** [August 20, 2021, 2:21am UTC](https://forums.developer.nvidia.com/t/gpio-control-on-xavier-nx-with-register-writes/187050/3 "2021-08-20T02:21:29Z")
hello msd11, please refer to python library, [Jetson GPIO](https://github.com/NVIDIA/jetson-gpio/tree/master/samples) for the samples that enables the use of Jetson’s GPIOs. you may also see [Topic 144550](https://forums.developer.nvidia.com/t/144550/), for several ways to access GPIOs. such as, kernel APIs, python scripts, C++ samples. thanks ---
**Author:** ![msd11](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@msd11](https://forums.developer.nvidia.com/u/msd11)\ **Post date:** [August 25, 2021, 1:06pm UTC](https://forums.developer.nvidia.com/t/gpio-control-on-xavier-nx-with-register-writes/187050/5 "2021-08-25T13:06:34Z")
Pardon me for late response but things have started to move in the regards of this issue. Python library again uses file operations. I wanted to be able to manipulate registers to control GPIOs i-e mmap operation with GPIO registers. To be able to play with GPIO registers, the first step will be to find out the register addresses. I used the links from Topic 144550 to write a script to read/modify xavier nx’s registers. On referring to [Xavier technical reference manual](https://developer.nvidia.com/embedded/downloads#?tx=%24product,jetson_agx_xavier), I tried to figure out the GPIO registers but it seemed little complicated. For an example, I was able to successfully figure out the address of PWM’s1 register and used mmap operations to turn it off. (1) Table in the section **3.1.2 System Address Map** (Page 42 ) mentions, PWM1 0x03280000 0x0328ffff SYSTEM (2) So, we have the start address of PWM1 register and now we need bit wise description of the register to be able to control the PWM. (3) Section 10.7.3 PWM Registers contains the bit wise description and using the info from the two sections mentioned above, I was able to manipulate the correct bit to turn off/onPWM. _This looks fine, but my goal is to be able to control GPIOs with register writes (lets say GPIO11 for example)._ Following the same steps as I did for PWM, I started looking for GPIO register addresses corresponding to GPIO11 in section 3.1.2. **Jetson\_Xavier\_NX\_Pinmux\_Configuration\_Template\_v1.06.xlsm** mentions full description for gpio11 as **GPIO3\_PQ.06**. So , thinking logically, I tried to locate GPIO3 in the section 3.1.2 of TRM but found numerous GPIO3s over there, namely, GPIO\_CTL0\_GPIO3, GPIO\_CTL1\_GPIO3, etc. **So how to figure out which address should I consult from all of these CTLX\_GPIO3** **addresses available ?** **and, if this is done then how to find GPIO register description just like there is one for PWM registers in section 10.7.3 of xavier’s TRM ?** ---
**Author:** ![JerryChang](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/jerrychang/32/14043_2.png) [@JerryChang](https://forums.developer.nvidia.com/u/JerryChang)\ **Post date:** [August 26, 2021, 6:37am UTC](https://forums.developer.nvidia.com/t/gpio-control-on-xavier-nx-with-register-writes/187050/6 "2021-08-26T06:37:55Z")
hello msd11, you may refer to `tegra19x-mb1-pinmux-p3668-a01.cfg` for the register address. for example, GPIO3\_PQ.06. `pinmux.0x02430030 = 0x00000000; # GPIO soc_gpio42_pq6` thanks ---
**Author:** ![msd11](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@msd11](https://forums.developer.nvidia.com/u/msd11)\ **Post date:** [August 26, 2021, 11:01am UTC](https://forums.developer.nvidia.com/t/gpio-control-on-xavier-nx-with-register-writes/187050/7 "2021-08-26T11:01:16Z")
Hey Jerry, thanks for replying ![image](https://global.discourse-cdn.com/nvidia/original/3X/2/c/2cffe2080e5ca459e1953b1423aad8ff1ec71b02.png) ![image](https://global.discourse-cdn.com/nvidia/original/3X/c/1/c1896e2c3e31ce841e67c985d512cea67e0c5447.png) I checked out the file you shared. As far as I could understand these registers are configuration registers for the pins, like configuring them as GPIO/SFIO etc. but these registers don’t offer the control over setting the GPIO high/low or setting the GPIO as input or output . How to locate these registers ? Can it be located using TRM or kernel source ? ---
**Author:** ![JerryChang](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/jerrychang/32/14043_2.png) [@JerryChang](https://forums.developer.nvidia.com/u/JerryChang)\ **Post date:** [August 30, 2021, 8:02am UTC](https://forums.developer.nvidia.com/t/gpio-control-on-xavier-nx-with-register-writes/187050/8 "2021-08-30T08:02:18Z")
hello msd11, you’ll need to refer to the `PADCTL_A0` for the base address, `0x02430000`, and, please adding offsets for the register address. ---
**Author:** ![msd11](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@msd11](https://forums.developer.nvidia.com/u/msd11)\ **Post date:** [August 31, 2021, 7:03am UTC](https://forums.developer.nvidia.com/t/gpio-control-on-xavier-nx-with-register-writes/187050/9 "2021-08-31T07:03:22Z")
Hello Jerry, If I am right then the registers which you have suggested are pinmux registers which are used to configure pin properties, But my use case is: I have allready configured the GPIO using file operations (as in [Jetson GPIO](https://github.com/NVIDIA/jetson-gpio/tree/master/samples)) and now all I need to do is to make the GPIO output value HIGH or LOW (i-e /sys/class/gpio/gpio266/value should read 1 or 0) and I need help in locating the register or a bit which I should toggle so that the output at corresponding GPIO turns HIGH or LOW. _ **Summary** :_ 1. configure a GPIO as output & other pinmux settings **—done** 2. Make the GPIO, HIGH **—need help** ---
**Author:** ![msd11](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@msd11](https://forums.developer.nvidia.com/u/msd11)\ **Post date:** [September 8, 2021, 6:27am UTC](https://forums.developer.nvidia.com/t/gpio-control-on-xavier-nx-with-register-writes/187050/10 "2021-09-08T06:27:16Z")
@JerryChang ---
**Author:** ![JerryChang](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/jerrychang/32/14043_2.png) [@JerryChang](https://forums.developer.nvidia.com/u/JerryChang)\ **Post date:** [September 8, 2021, 7:17am UTC](https://forums.developer.nvidia.com/t/gpio-control-on-xavier-nx-with-register-writes/187050/12 "2021-09-08T07:17:43Z")
can you toggle the pin as following to configure it as high? `echo out > direction && echo 1 > value` ---
**Author:** ![nadeemm](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/nadeemm/32/367020_2.png) [@nadeemm](https://forums.developer.nvidia.com/u/nadeemm)\ **Post date:** [October 18, 2021, 6:40pm UTC](https://forums.developer.nvidia.com/t/gpio-control-on-xavier-nx-with-register-writes/187050/14 "2021-10-18T18:40:40Z")
Closed on October 18, 2021, 6:40pm UTC