I am looking to get a parallel data output from the Jetson TX2. As pretty much every connector on the TX2 uses a serial format, I was thinking of using the GPIO pins as a parallel output. In this case, it would use 12-16 GPIO pins as data pins which each represent different bit positions of a single data output at a time. Each of these pins would then be connected to a breadboard with a resistor ladder, allowing for a digital to analog conversion. I was wondering if anybody has implemented this before, not necessarily the DAC part, but just the parallel output in general. I was also wondering how fast the GPIO pins can be updated, as that would limit the output speed in this case.
there’re two groups of GPIOs, Main and AON GPIOs. you may have each GPIO controller owned by different masters.
you may also refer to TRM.
please check [8.9 GPIO Controller] within [CHAPTER 8: MULTI-PURPOSE I/O PINS AND PIN MULTIPLEXING (PINMUXING)] for more details.
here’s a discussion thread you may refer to, gpio interrupts from user space.
This may prove to be very difficult based on the jitter/synchronization of the update to the new value across all of the GPIOs. Unlike many modern SoCs, NVIDIA has chosen to implement the GPIO control with each GPIO getting a separate address in memory, and with no GPIO bank support to allow simultaneous updates of multiple GPIOs at once. This means doing this from userspace with the existing sysfs GPIO interface would be impossible without a particular GPIO acting as a clock and synchronizing the value of all the GPIOs to the external hardware interface. The best update you could hope for would be to write something that lives in the kernel and disables interrupts immediately before writing out the appropriate values to all of the GPIO addresses and then re-enables interrupts. There will still be some amount of delay between the memory/GPIO controller synchronization of bit 0 with say bit 15, updated last. Depending on your hardware interface consuming the 16-bits of parallel data, this delay might be perfectly acceptable OR it could register an erroneous value/state of the parallel data.
If you have the ability to add extra hardware and require tight synchronization of the updated parallel interface, then the best option would be to add flip-flops (or latches) to each of the 12-16 GPIO outputs and control the synchronization of the new value to the external interface with one additional GPIO acting as the clock/update signal for all of the latches. The extra hardware eliminates the erroneous value/state problem with delays between updating bit 0 and bit 15, but does not help increase the maximum frequency that you can update the entire parallel interface to a new value. To increase the update rate you will most likely need to use the SPE/Cortex-R and write some dedicated assembly code to efficiently update to new parallel values.