# GPIO pull-down resistors **URL:** \ **Category:** Jetson AGX Xavier\ **Created:** [July 21, 2019, 3:51pm UTC](https://forums.developer.nvidia.com/t/gpio-pull-down-resistors/78424 "2019-07-21T15:51:15Z")\ **Posts on this page:** 11\ **Page:** 1
**Author:** ![WasabiFan](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/wasabifan/32/101760_2.png) [@WasabiFan](https://forums.developer.nvidia.com/u/WasabiFan)\ **Post date:** [July 21, 2019, 3:51pm UTC](https://forums.developer.nvidia.com/t/gpio-pull-down-resistors/78424/1 "2019-07-21T15:51:15Z")
From looking at the Xavier carrier board design file schematic and the carrier board specification document, GPIO pins such as board pins 22 and 15 should have 1Mohm pull-down resistors. Yet when using the Jetson.GPIO library they seem to behave as if they don’t have such resistors, and when I measure the resistance between one of those pins and ground I see no connection at all. What am I missing here? How do I use GPIOs with internal pull-down resistors? ---
**Author:** ![JerryChang](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/jerrychang/32/14043_2.png) [@JerryChang](https://forums.developer.nvidia.com/u/JerryChang)\ **Post date:** [July 22, 2019, 7:25am UTC](https://forums.developer.nvidia.com/t/gpio-pull-down-resistors/78424/2 "2019-07-22T07:25:51Z")
hello WasabiFan, please download [Pinmux](https://developer.nvidia.com/embedded/downloads#?search=pinmux) spreadsheets via Jetson Download Center, and you might refer to [Jetson AGX Xavier MB1 Platform Configuration](https://docs.nvidia.com/jetson/archives/l4t-archived/l4t-322/index.html#page/Tegra%2520Linux%2520Driver%2520Package%2520Development%2520Guide%2Fmb1_platform_config_xavier.html%23) chapter for configure GPIOs. thanks ---
**Author:** ![WasabiFan](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/wasabifan/32/101760_2.png) [@WasabiFan](https://forums.developer.nvidia.com/u/WasabiFan)\ **Post date:** [July 22, 2019, 12:07pm UTC](https://forums.developer.nvidia.com/t/gpio-pull-down-resistors/78424/3 "2019-07-22T12:07:13Z")
Can you expand on that? I don’t understand what you are suggesting I do to fix the problem. I’ve already looked at the pinmux spreadsheet, but it also says that the pin has a pull-down resistor (I assume the configuration shown in the spreadsheet is the default one for the Xavier). Are you saying I should be changing the configuration? ---
**Author:** ![JerryChang](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/jerrychang/32/14043_2.png) [@JerryChang](https://forums.developer.nvidia.com/u/JerryChang)\ **Post date:** [August 1, 2019, 10:00am UTC](https://forums.developer.nvidia.com/t/gpio-pull-down-resistors/78424/4 "2019-08-01T10:00:54Z")
hello WasabiFan, please modify the pinmux spreadsheet, customize the content below “Filled in by Customers” column. once you finish the modification, you’ll need to click the [Generate DT file] to output new gpio and pinmux device tree files, please also check [Jetson AGX Xavier MB1 Platform Configuration chapter] for the steps to create the cfg file. you’ll need to re-flash the board with the new cfg files to make the change. thanks ---
**Author:** ![WasabiFan](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/wasabifan/32/101760_2.png) [@WasabiFan](https://forums.developer.nvidia.com/u/WasabiFan)\ **Post date:** [August 1, 2019, 10:14am UTC](https://forums.developer.nvidia.com/t/gpio-pull-down-resistors/78424/5 "2019-08-01T10:14:30Z")
I don’t want to change the device tree configuration: I want to understand the default configuration. Why do the data sheets appear to incorrectly report the default pin configuration, and where can I find correct information? ---
**Author:** ![JerryChang](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/jerrychang/32/14043_2.png) [@JerryChang](https://forums.developer.nvidia.com/u/JerryChang)\ **Post date:** [August 2, 2019, 2:27am UTC](https://forums.developer.nvidia.com/t/gpio-pull-down-resistors/78424/6 "2019-08-02T02:27:50Z")
hello WasabiFan, you could check the default configuration as below cfg file, for example, ```auto $OUT/Linux_for_Tegra/bootloader/tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg ``` you might also check [Jetson AGX Xavier Developer Kit Carrier Board Design Files](http://developer.nvidia.com/embedded/dlc/jetson-xavier-developer-kit-carrier-board-design-files-b03), for carrier board design files. thanks ---
**Author:** ![WasabiFan](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/wasabifan/32/101760_2.png) [@WasabiFan](https://forums.developer.nvidia.com/u/WasabiFan)\ **Post date:** [August 8, 2019, 3:12pm UTC](https://forums.developer.nvidia.com/t/gpio-pull-down-resistors/78424/7 "2019-08-08T15:12:48Z")
I understand that you’re trying to answer my question but you aren’t giving the relevant information. Specifically, what document and page should I look at to identify whether a particular pin has a pull-up or pull-down resistor? Please show me the document and page. I don’t want to be crawling through config files. Checking the live configuration on a particular Jetson might happen to work, but the behavior should be documented without having to boot up and connect to the device. The design files are a ZIP folder of dozens of documents, and I haven’t been able to find one which aligns with the apparent behavior of the board. ---
**Author:** ![JerryChang](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/jerrychang/32/14043_2.png) [@JerryChang](https://forums.developer.nvidia.com/u/JerryChang)\ **Post date:** [August 13, 2019, 1:53am UTC](https://forums.developer.nvidia.com/t/gpio-pull-down-resistors/78424/8 "2019-08-13T01:53:49Z")
hello WasabiFan, had you open pinmux spreadsheet for checking? you’ll found PD/PU configuration in the pinmux spreadsheet. thanks ---
**Author:** ![WasabiFan](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/wasabifan/32/101760_2.png) [@WasabiFan](https://forums.developer.nvidia.com/u/WasabiFan)\ **Post date:** [August 13, 2019, 9:57am UTC](https://forums.developer.nvidia.com/t/gpio-pull-down-resistors/78424/9 "2019-08-13T09:57:40Z")
Yes. GPIO17 (pin 22 on the main GPIO header) is listed as having a 100k pull-down resistor in the spreadsheet, but it doesn’t behave like it has a pull-down resistor in practice when I tested it. ---
**Author:** ![snarky](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/snarky/32/10446_2.png) [@snarky](https://forums.developer.nvidia.com/u/snarky)\ **Post date:** [August 13, 2019, 6:44pm UTC](https://forums.developer.nvidia.com/t/gpio-pull-down-resistors/78424/10 "2019-08-13T18:44:37Z")
What code did you use to test it? What hardware did you use to test it? The combination of MPIO / Pinmux / GPIO mux / Rail configurations / Voltage translation on carrier boards is somewhat bewildering … ---
**Author:** ![TomNVIDIA](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/tomnvidia/32/14181_2.png) [@TomNVIDIA](https://forums.developer.nvidia.com/u/TomNVIDIA)\ **Post date:** [October 18, 2021, 6:24pm UTC](https://forums.developer.nvidia.com/t/gpio-pull-down-resistors/78424/11 "2021-10-18T18:24:07Z")
Closed on October 18, 2021, 6:24pm UTC