After upgrading the JP4.6 version code to JP5.1.1 above, and then the PCIE to NIC chip I225 needs to pull up the GPIO to power, but now after porting the corresponding things to the past, it is found that Our GPIO is pulled up behind the pcie loading platform Driver and device Driver, so the chip cannot be scanned. Have you encountered similar problems before? How did you solve it?
I’m using a carrier we made ourselves.
What did you do for porting these?
Which GPIO are you using?
Have you tried the AGX Xavier devkit with the same behavior?
I mainly enable the corresponding Driver, but due to the hardware circuit design, if I want to enable the PCIE to network port chip, I have to pull up this GPIO to supply power to the chip at 3.3V. But now I use the definition in the following picture, I will find that the time for pulling up GPIO is after the PCIE Driver scan. Look at the next pictures.
I use TEGRA194_MAIN_GPIO, which I haven’t tried in the development kit because I don’t have one around at the moment.
What I’m more wondering is, how should I go about pulling up the GPIO before the PCIE Platform Driver loads, which seems to involve the order in which the driver loads?
Have you tried using pinmux spreadsheet to configure these pins (PQ.01, PT.05, PN.00) to high as default?
Do you mean to perform the following operations in the pinmux form and then flash them to xavier?
Yes, if it doesn’t work, please try to set it as “Drive 1”.
Now I can check my pci device normally !
Thank you so much for your help!
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