GPIOs (port/pin/wire/register) available for sw & hw co-design and measurement

Please provide the following info (check/uncheck the boxes after creating this topic):
Software Version
DRIVE OS Linux 5.2.6
DRIVE OS Linux 5.2.6 and DriveWorks 4.0
DRIVE OS Linux 5.2.0
DRIVE OS Linux 5.2.0 and DriveWorks 3.5
NVIDIA DRIVE™ Software 10.0 (Linux)
NVIDIA DRIVE™ Software 9.0 (Linux)
other DRIVE OS version

Target Operating System

Hardware Platform
NVIDIA DRIVE™ AGX Xavier DevKit (E3550)
NVIDIA DRIVE™ AGX Pegasus DevKit (E3550)

SDK Manager Version

Host Machine Version
native Ubuntu 18.04

Being a solid/sealed DriveAGX unit, is there any GPIOs (or other software writeable port/wire/pin/register) available for DriveOS/DriveWorks software to set/write in the software, and also expose these GPIOs (port/wire/pin/register) signals outside of the DriveAGX box, so that they can be connected to the oscilloscope‘s probes for more accurate high-resolution measurement? For example:

  • Interrupt latency measurement from hw int trigger to driver ISR code

  • Sensor image processing pipeline: hw sensor rx trigger → ISP int → image data preprocess → inference on CUDA/Tensor/DLA → postprocess

Dear @hfkou,
AFAIK, the requested items can not be done on the board. Let me check internally on this.

Hi, @hfkou

May I know which kind of DRIVE release you are using? SDK or PDK. SDKs supported in this forum are more for application development.

Doesn’t matter SDK or PDK, if we want to deep dive into the sw hw co-design level to measure the system latency, for example DriveOS real-time behavior on the silicon chip, this kind of low level IOs are required, so please help checking internally NV developers for a potential solution if it is possible, thanks.

understand it but this isn’t in the support scope of devzone release and this forum.
I would suggest you contact your nvidia rep and see if any next-level engagement can help.

The below topic may not be directly related to what you’re looking for. But just FYR.

Find the following GPIO information on Drive platforms:

Also the outside HW adapter

In order to write/read to these GPIOs, could NV please point to the DriveOS code or provide some guideline direction on the GPIO R/W operation?

Relevant materials for GPIO programming aren’t available on our developer site but only on nvonline for specific customers. It’s also not in the support scope here.

I would suggest you contact your nvidia representative, or if you have PDK access, please get support from the channel. Thanks.