Re-post of a reply in another thread - I think it should be seen by the forum admins.
To all at nVidia:
We understand that we as the designers are responsible for our own products - this doesn’t stop other companies that offer modules like this from providing some guidance or suggestions based on their own experience in making their evaluation kits.
Altera/Intel has a PDN tool that will literally tell you if you have reached your target impedance in providing power to their SoC.
Other developers of SoM carrier modules will often put notes in the carrier design guide like:
This net includes a 0.1uF cap. Add the bulk capacitance necessary to meet the USB specification for your device application. This will generally be 1uF to 100uF and is specific to the mode of operation for the USB endpoint. Switching supplies are recommended as the best design practice. These reduce wasted power and result in a better product design. As temperature increases in a design, the cooling requirements become more onerous. Higher temperatures also increase part failures and reduce the MTBF of a design.
You’ve literally offered zero guidance at all - no specs on ripple, on module capacitance, even the sequencing and power-down information is nearly incoherent.
Then when folks come here and ask for help you just say ‘look at the eval board’ which by the way, ‘is not intended to be a product’.
So if the actual designers of the module can’t offer guidance or insight as to how to make a robust/rugged product with their own product, how are we supposed to have a better idea?
You are literally offering no support to basic hardware questions that any seasoned engineer would ask, and I myself asked and gave up when working directly with you.
These will be as successful as you are willing to support designers in using them, or people will give up and find a company that works harder to make designers have an easier time designing a very complex module into what is almost assuredly a more complex product.
Xilinx has like 10,000 pages of documentation on a single MPSoC family - you’ve got like 120 pages on designing hardware around this SoM. I hope you understand how shockingly light your support and documentation are.