Hardware References For NVidia Developers

Hello,

I am asking here because I am not sure where this information is.

I need resources to aid in the development of PCB’s using NVidia’s processors and GPU’s.
A PDF of a schematic or existing board is not what I am asking for.

Does NVidia have any PCB development resources for people involved in proto-type development?

Thanks In Advance,
John W.

I’ve found that one of nVidia’s hardware suppliers has good information on this:
http://developer.toradex.com/hardware-resources/arm-family/carrier-board-design

Wow, all in Altium too - I will take look at this.

Any more you may know about?

Thanks,
John W.

Design guides for PCIe in general are good, although I don’t have a URL off the top of my head. I’ve been through a lot of RF theory for antennas and transmission lines, and after awhile it starts to show that this applies. So it may not appear to be applicable, but you may want to invest in some RF background.

Take for example PCIe RX/TX (data) lanes. The way the standards work the initial outbound signal is insufficient for reliable signals…at the end of the lane there is a reflection which comes back and adds to the initial outbound signal…forward and reflected add (1:1 standing wave ratio if you look at radio transmission line theory) and this is what is required to fully utilize PCIe data lane speeds. If traces on each side of the LVDS pair are not uniform length, then the reflection may not be additive or may be slowed and data becomes unreliable (forward+reflected timing relative to clock is off). This is standard transmission line theory and is a general theme on any high performance PC trace design.

There are also controllable slew rates to adjust traces to particular impedances (see the TRM for TK1…some are programmable, others are best guess). This is basically antenna theory and maximum power transfer theorem. Traces to items need uniform trace lengths when acting as a transmission line; traces also need to absorb power at the far end for the equivalent of an antenna…thus you see requirements for trace thickness, trace spacing, and capacitances. Many schematic capture programs understand this, but it makes a lot more sense a lot faster if you have that antenna and transmission line theory. When you start reading those docs from Toradex things become much more obvious much faster.

I presume you’d need to sign an NDA with NVIDIA in order to get access to hardware documentation (datasheet, design guide etc).

The TRM and other docs people are commonly using here require a login, which in turn has terms. It isn’t a big deal though, start by getting a login somewhere like here:
https://developer.nvidia.com/jetson-tk1-support

Much of the PCB design is done via schematic capture programs which understand impedance. The TRM for Tegra K1 will show expected impedance, although it is a long read. The Gerber files and other PCB files were generated by such a program.

Key words to search for in the TRM (and which interact with schematic capture) are “slew” and “impedance”. Just search for those in the TRM while providing details to your schematic capture software.

Correct me if I’m wrong but Tegra K1 TRM is basically a programming manual, it doesn’t contain any schematic design not PCB layout guidelines.

This is mostly correct. However, the TRM does show information on impedance/slew related to specific traces…those need to be followed when building the PCB. Schematic capture can be told to use any impedance, it just might not be correct. If you design this by hand, then you still need to basically build RF savvy traces which match the Tegra requirements. So far as I know most people use schematic capture and then might hand tweak rather than the other way around. Other than what the Tegra124 requires for impedance and timing, none of this design requires anything from nVidia.