HDMI FCC certification fail

Hi, our device cann’t pass FCC, the HDMI swing is bigger than standard. The FCC need less than 500mv, but we are ablout 700mv. And we check your demo board, it is about 800mv. So How should we config it.

Hi, for custom design of HDMI part, please refer to the Design Guide to make sure schematic and routing are correct. And also you can refer to Tuning Guide for more info.



if we want to modify the hdmi out swing by software, what should we do ?

Do you mean single-ended or differentially swing? The spec is 500 mV ± 100 mV, single-ended, or 1000 mV ± 200 mV differentially.

Hi , if we modify single-ended swing, what should we do?

Follow the tuning guide in previous comment to try different drive current and PREEMPHASIS

Could you give us detailde method? It means modify codes ?
For example: we now single-ended swing is about 700mv, how to change to 500mv in code?


The tuning guide will tell you the register and the mean of each bit. Use devmem2 or busybox devmem to tune the register.

But I don’t know the swing’s relationship to registers.
The tuning guide just the register explain.

You need to tune the register value with devmem2 or busybox devmem accordingly and observe the swing change so as to find out which value is what you want.

we need your help, in the doc, there are many registers , we don’t know which register need to try and don’t know what the register bit value should be? we think you should have the example for us, it is difficult for us.

As listed in doc, there are not many registers. And the register name has told you what it is for. Like SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_1 and SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_1, please tune the value of them.

Also as listed in doc, it says: 6. If the eye diagram fails, adjust the drive strengths and pre-emphasis settings. Refer to the registers section.

you mean we just tune SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_1 and SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_1 , the two registers?

I used devmem2 read the register value:
SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_1 0x54580138 0x2D303430
what are the default values for the two registers?
The 0x54580148 is 0x0, does it mean we didn’t support PREEMPHASIS0?

Yes by the two registers. You can get the default value in the table in guide doc.

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