We use the FPGA for HDMI video to MIPI CSI, video format YUV422, resolution 1920x1080xP60.
HDMI video 1920x1080xP60 --> FPGA --> MIPI CSI 4 Lanes / YUV422
The FPGA convert the HDMI video into MIPI CSI format and is connected to MIPI CSI interface 4 Lanes(CSI A, CSI B) of TX2.
As below block diagram:


We reference to TC358840 and remove all of the i2c part as dummy HDMI FPGA video driver.

Device Tree:
[ hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-c03-00-base.dts ]
tegra186-quill-p3310-1000-c03-00-base.dts.TS358840_parts.txt (8.3 KB)

dmesg_1120.txt (180.0 KB)

enable trace log command:
trace_command_1120.txt (499 Bytes)

the trace log:
trace_log_1120.txt (475.1 KB)

I can see /dev/video0 device, but I can’t get output video images from v4l2-ctl -d /dev/video0 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=3.
How to verify NVCSI get vaild MIPI data from FPGA in trace log on TX2?

The trace log show didn’t receive any validate data.
At least should have some FS/FE … tag in the trace log. Have a reference to below link for the trace long information.

How to analysis the trace log to know the current MIPI CSI fail root cause?
CSI lane mode, lane speed, csi port incorrect? CSI EC parameter no match?

For those configure you may need to enable the debug print from the csi4_fops.c/vi4_fops.c

I add vi4_fops.c, csi4_fops.c, csi.c, nvcsi.c to debug print.

enable trace command:

echo 1 > /sys/kernel/debug/tracing/tracing_on
echo 30720 > /sys/kernel/debug/tracing/buffer_size_kb
echo 1 > /sys/kernel/debug/tracing/events/tegra_rtcpu/enable
echo 1 > /sys/kernel/debug/tracing/events/freertos/enable
echo 2 > /sys/kernel/debug/camrtc/log-level
echo 1 > /sys/kernel/debug/tracing/events/camera_common/enable
echo > /sys/kernel/debug/tracing/trace

echo file vi2_fops.c +p > /sys/kernel/debug/dynamic_debug/control
echo file csi2_fops.c +p > /sys/kernel/debug/dynamic_debug/control

echo file vi4_fops.c +p > /sys/kernel/debug/dynamic_debug/control
echo file csi.c +p > /sys/kernel/debug/dynamic_debug/control
echo file csi4_fops.c +p > /sys/kernel/debug/dynamic_debug/control
echo file nvcsi.c +p > /sys/kernel/debug/dynamic_debug/control

trace log:
trace_log_1120_4.txt (188.7 KB)

dmesg_1120_4.txt (348.2 KB)

You can see the configure in the kernel message like using csi port 0 and 4 lane and others. You can check if those configure is correct or not. If there’s no problem that tell the output source may have problem. You may need to probe the MIPI signal to make sure of it.

Could you give some realy trace log sample to let me confirm configure is working about at least should have some FS/FE … tag in the trace log?
Thank you.

Have a reference to below

   kworker/1:1-847   [001] .......   244.899098: rtcpu_vinotify_event: tstamp:8049311928 tag:FS channel:0x02 frame:4 vi_tstamp:8049307147 data:0x00000014
     kworker/1:1-847   [001] .......   244.950066: rtcpu_vinotify_event: tstamp:8049785913 tag:ATOMP_FS channel:0x00 frame:4 vi_tstamp:8049307150 data:0x00000000
     kworker/1:1-847   [001] .......   244.950069: rtcpu_vinotify_event: tstamp:8049786046 tag:CHANSEL_PXL_SOF channel:0x23 frame:4 vi_tstamp:8049308270 data:0x00000001
     kworker/1:1-847   [001] .......   244.950070: rtcpu_vinotify_event: tstamp:8049786191 tag:RESERVED_19 channel:0x23 frame:4 vi_tstamp:8469781056 data:0x08020001
     kworker/1:1-847   [001] .......   244.950071: rtcpu_vinotify_event: tstamp:8050273952 tag:CHANSEL_PXL_EOF channel:0x23 frame:4 vi_tstamp:8050122378 data:0x02cf0002
     kworker/1:1-847   [001] .......   244.950072: rtcpu_vinotify_event: tstamp:8050274096 tag:ATOMP_FRAME_DONE channel:0x23 frame:4 vi_tstamp:8050122401 data:0x00000000
     kworker/1:1-847   [001] .......   244.950073: rtcpu_vinotify_event: tstamp:8050274220 tag:RESERVED_19 channel:0x23 frame:4 vi_tstamp:8495820032 data:0x02020001
     kworker/1:1-847   [001] .......   244.950074: rtcpu_vinotify_event: tstamp:8050274363 tag:FE channel:0x02 frame:4 vi_tstamp:8050122402 data:0x00000024
     kworker/1:1-847   [001] .......   244.950074: rtcpu_vinotify_event: tstamp:8050274491 tag:ATOMP_FE channel:0x00 frame:4 vi_tstamp:8050122404 data:0x00000000
     kworker/1:1-847   [001] .......   244.950099: rtcpu_vinotify_event: tstamp:8050762427 tag:FS channel:0x02 frame:1 vi_tstamp:8050348720 data:0x00000014
     kworker/1:1-847   [001] .......   244.950100: rtcpu_vinotify_event: tstamp:8050762559 tag:ATOMP_FS channel:0x00 frame:1 vi_tstamp:8050348723 data:0x00000000
     kworker/1:1-847   [001] .......   244.950101: rtcpu_vinotify_event: tstamp:8050762716 tag:CHANSEL_PXL_SOF channel:0x23 frame:1 vi_tstamp:8050349843 data:0x00000001
     kworker/1:1-847   [001] .......   244.950101: rtcpu_vinotify_event: tstamp:8050762841 tag:RESERVED_19 channel:0x23 frame:1 vi_tstamp:8503095616 data:0x08020001
     kworker/1:1-847   [001] .......   244.950102: rtcpu_vinotify_event: tstamp:8051167052 tag:CHANSEL_PXL_EOF channel:0x23 frame:1 vi_tstamp:8051163951 data:0x02cf0002
     kworker/1:1-847   [001] .......   244.950103: rtcpu_vinotify_event: tstamp:8051167175 tag:ATOMP_FRAME_DONE channel:0x23 frame:1 vi_tstamp:8051163973 data:0x00000000
     kworker/1:1-847   [001] .......   244.950103: rtcpu_vinotify_event: tstamp:8051167318 tag:RESERVED_19 channel:0x23 frame:1 vi_tstamp:8529150336 data:0x02020001
     kworker/1:1-847   [001] .......   244.950104: rtcpu_vinotify_event: tstamp:8051167443 tag:FE channel:0x02 frame:1 vi_tstamp:8051163978 data:0x00000024
     kworker/1:1-847   [001] .......   245.001064: rtcpu_vinotify_event: tstamp:8051641138 tag:ATOMP_FE channel:0x00 frame:1 vi_tstamp:8051163979 data:0x00000000

Our FPGA output MIPI 4 Lanes to CSI-A and CSI-B.
Our schematic connect FPGA MIPI CSI clock to CSI-A-CLK on TX2.

May I confirm that FPGA MIPI CSI clock shoud connect to CSI-A-CLK or CSI-B-CLK on TX2?

Should connect to CSI-A-CLK

How to select CSI data route to ISP or memory?

Do you have documents to introduct the NVCSI relation configure?

We don’t know how to configure :
-NVCSI to 1x4lanes?
-NVCSI data format to YUV4222-8bit or YUV420-8bit?
-NVCSI setup to DPHY mode or CPHY mode?

Have a check the sensor programing guide.


Yes, I had read this sensor programing guide.
But this document only introduction device tree setting, and I can’t understand how to setting relation register and detail flow.

Does these NVCSI register are setup by I2C interface?

The sensor i2c REG setting need consult with vendor.

I know read and write sensor register by I2C.
But my question is read/write the NVCSI regsiter of TX2 by I2C?

Why do you need to read/write nvcsi/vi reg. The nvcsi/vi configure are depend on device tree.
NVCSI/VI REG are programing by the csi/vi kernel driver.
Have a check the csi4_fops.c/vi4_fops.c to know the detail.

Because I need to know these NVCSI/VI register setting, and update it to my driver in startup setting.

In the another hand, May I to know the root cause of “PXL_SOF syncpt timeout! err = -11”?
tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channelkernel_log_1080P60_1202.txt (488.8 KB)
trace_log_1080P60_1202.txt (572.0 KB)

PXL_SOF cause by the NVCSI/VI didn’t receive any validate data from the bus.
You may need to probe the MIPI signal to make sure the sensor output data as MIPI spec.

This FPGA daughter board is working on other SoC platform.
But same FPGA daugter board is un-validate data on TX2 platform.