Thanks @WayneWWW this is good information and I will work with the engineers and update on the progress.
@WayneWWW I have received a response from the engineers that includes images and files in an email. I will post the text here.
We are working on connecting a 480x480 pixel display with the st7701 controller to the Jetson Nano P3448-0002 moduleP3449-0000 carrier board via mipi-dsi. We implemented the setting of the dsi interface and checked the dsi contacts with an oscilloscope. We saw command pulse sequences and frequencies, just like the Linux kernel in dmesg (IMG_20230906_183439.jpg) issues messages that the interface is connected. Therefore, dsi works correctly. The backlight driver has not yet been implemented, so we have enabled the backlight of the display through the gpio port node as follows on the picture IMG_20230906_183735.jpg We defined the reset pin in the file tegra210-porg-gpio-p3448-0002-b00.dtsi as an output pin with a value of 0.After turning on the power, we saw on the oscilloscope that the reset pin became a logical one and there were no switching of this pin.
Our device tree in file tegra210-porg-p3448-common.dtsi
Display settings in panel-a-wxga-8-0.dtsi
Gpio settings in tegra210-porg-gpio-p3448-0002-b00.dtsi
We implemented the display initialization according to the set of commands sent to us by the display manufacturer in file 2.76IPS+ST7701 initial code.txt
He also sent a datasheet and a description of the settings in files Z28008-P24-ZC1.pdf and porch.jpg
We also implemented initialization commands and timings in panel-a-wxga-8-0.dtsi. However, there is no image on the display. We think that the problem with the pin is reset, or in the specific display settings for the Jetson platform.
Could you help us to solve this problem?
Hi,
Just to clarify.
-
Does that reset pin have anything to do with that pwm pin? I am just not quite sure about your comment that you said “dsi works” and then told me about pwm and then said reset pin is not working.
-
Could you check kernel/nvidia/drivers/video/tegra/dc/panel/board-panel.c driver code and see if that nvidia,panel-rst-gpio really got reading from device tree and got toggled?
Hi Wayne,
Thank you for the response. Unfortunately, no files were attached to the last post, so I will duplicate the post for a better understanding of our situation.
"We are working on connecting a 480x480 pixel display with the st7701 controller to the Jetson Nano P3448-0002 moduleP3449-0000 carrier board via mipi-dsi.
We implemented the setting of the dsi interface and checked the dsi contacts with an oscilloscope. We saw command pulse sequences and frequencies, just like the Linux kernel in dmesg issues messages that the interface is connected.
Therefore, dsi works correctly. The backlight driver has not implemented, so we have enabled the backlight of the display through the gpio port node
We defined the reset pin C4 in the file tegra210-porg-gpio-p3448-0002-b00.dtsi as an output pin with a value of 0.
#include <dt-bindings/gpio/tegra-gpio.h>
/ {
gpio: gpio@6000d000 {
gpio-init-names = "default";
gpio-init-0 = <&gpio_default>;
gpio_default: default {
gpio-input = <
TEGRA_GPIO(A, 5)
TEGRA_GPIO(X, 4)
TEGRA_GPIO(X, 5)
TEGRA_GPIO(X, 6)
TEGRA_GPIO(Y, 1)
TEGRA_GPIO(V, 1)
TEGRA_GPIO(Z, 2)
TEGRA_GPIO(H, 2)
TEGRA_GPIO(H, 5)
TEGRA_GPIO(H, 6)
TEGRA_GPIO(I, 1)
TEGRA_GPIO(CC, 4)
>;
gpio-output-low = <
TEGRA_GPIO(S, 7)
TEGRA_GPIO(T, 0)
TEGRA_GPIO(Z, 3)
TEGRA_GPIO(H, 0)
TEGRA_GPIO(H, 3)
TEGRA_GPIO(H, 4)
TEGRA_GPIO(H, 7)
TEGRA_GPIO(I, 0)
TEGRA_GPIO(I, 2)
TEGRA_GPIO(C, 4)
>;
gpio-output-high = <
TEGRA_GPIO(A, 6)
TEGRA_GPIO(X, 3)
TEGRA_GPIO(CC, 7)
>;
};
};
};
After turning on the power, we saw on the oscilloscope that the reset pin became a logical one and there were no switching of this pin."
Our device tree in file tegra210-porg-p3448-common.dtsi
/*
* arch/arm64/boot/dts/tegra210-porg-p3448-common.dtsi
*
* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
*/
/dts-v1/;
/memreserve/ 0x80000000 0x00020000;
#include <t210-common-platforms/tegra210-common.dtsi>
#include <tegra210-soc/tegra210-sdhci.dtsi>
#include <t210-common-platforms/tegra210-thermal-nct72-p2530.dtsi>
#include <tegra210-soc/tegra210-thermal-Tboard-Tdiode.dtsi>
#include "porg-platforms/tegra210-porg-power-tree-p3448-0000-a00.dtsi"
#include "porg-platforms/tegra210-pinmux-drive-sdmmc-common.dtsi"
#include "porg-platforms/tegra210-porg-pwm-fan.dtsi"
#include <t210-common-platforms/tegra210-ers-hdmi-e2190-1100-a00.dtsi>
#include <t210-common-platforms/tegra210-dp.dtsi>
#include <t210-common-platforms/tegra210-thermal-userspace-alert.dtsi>
#include "porg-platforms/tegra210-porg-thermal.dtsi"
#include "porg-platforms/tegra210-porg-thermal-fan-est.dtsi"
#include "porg-platforms/tegra210-porg-keys-p3448-0000-a00.dtsi"
#include <dt-bindings/iio/meter/ina3221x.h>
#include <tegra210-soc/tegra210-audio.dtsi>
#include "porg-platforms/tegra210-porg-cpufreq.dtsi"
#include "porg-platforms/tegra210-porg-powermon-p3448-0000-a00.dtsi"
#include "porg-plugin-manager/tegra210-porg-eeprom-manager.dtsi"
#include "porg-plugin-manager/tegra210-porg-plugin-manager.dtsi"
#include <tegra210-soc/mods-simple-bus.dtsi>
#include "porg-platforms/tegra210-porg-extcon-p3448-0000-a00.dtsi"
#include "porg-platforms/tegra210-porg-pcie.dtsi"
#include "porg-platforms/tegra210-porg-prods.dtsi"
#include "porg-platforms/tegra210-porg-super-module-e2614.dtsi"
#include <panels/panel-a-wxga-8-0.dtsi>
/ {
nvidia,boardids = "3448";
nvidia,proc-boardid = "3448";
nvidia,pmu-boardid = "3448";
nvidia,fastboot-usb-pid = <0xb442>;
chosen {
nvidia,tegra-porg-sku;
stdout-path = "/serial@70006000";
nvidia,tegra-always-on-personality;
no-tnid-sn;
bootargs = "earlycon=uart8250,mmio32,0x70006000";
};
cpus {
cpu@0 {
clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
<&tegra_car TEGRA210_CLK_CCLK_LP>,
<&tegra_car TEGRA210_CLK_PLL_X>,
<&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
<&tegra_clk_dfll>;
clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
clock-latency = <300000>;
};
};
rollback-protection {
status = "okay";
};
host1x {
/* Camera unit clocks */
assigned-clocks = <&tegra_car TEGRA210_CLK_EXTERN3>,
<&tegra_car TEGRA210_CLK_CILE>,
<&tegra_car TEGRA210_CLK_CILCD>,
<&tegra_car TEGRA210_CLK_CILAB>,
<&tegra_car TEGRA210_CLK_VI_I2C>,
<&tegra_car TEGRA210_CLK_CLK_OUT_3_MUX>,
<&tegra_car TEGRA210_CLK_VI>,
<&tegra_car TEGRA210_CLK_ISP>,
<&tegra_car TEGRA210_CLK_ISPB>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_EXTERN3>,
<&tegra_car TEGRA210_CLK_PLL_C>,
<&tegra_car TEGRA210_CLK_PLL_C>,
<&tegra_car TEGRA210_CLK_ISP>;
assigned-clock-rates = <24000000>,
<102000000>,
<102000000>,
<102000000>,
<102000000>,
<24000000>,
<408000000>,
<408000000>,
<0>;
/* tegradc.0 */
dc@54200000 {
status = "okay";
nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
nvidia,emc-clk-rate = <300000000>;
nvidia,cmu-enable = <1>;
nvidia,fb-bpp = <32>; /* bits per pixel */
nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
nvidia,dc-or-node = "/host1x/sor1";
nvidia,dc-connector = <&sor1>;
win-mask = <0x7>; /* Assign only wins A/B/C */
};
dc@54240000 {
status = "okay";
nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
nvidia,emc-clk-rate = <300000000>;
nvidia,fb-bpp = <32>; /* bits per pixel */
nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
nvidia,dc-or-node = "/host1x/dsi";
nvidia,dc-connector = <&dsi>;
/* DSI supplies */
avdd_dsi_csi-supply = <&max77620_sd3>;
avdd_lcd-supply = <&battery_reg>;
dvdd_lcd-supply = <&battery_reg>;
vdd_lcd_bl_en-supply = <&battery_reg>;
vdd_lcd_bl-supply = <&battery_reg>;
win-mask = <0x7>; /* Assign only wins A/B/C */
};
dsi {
nvidia,dsi-controller-vs = <DSI_VS_1>;
status = "okay";
nvidia,active-panel = <&panel_a_wxga_8_0>;
//nvidia,dsi-csi-loopback;
panel-a-wxga-8-0 {
status = "okay";
nvidia,panel-rst-gpio = <&gpio TEGRA_GPIO(C, 4) 0>; /* PC4 */
nvidia,panel-bl-pwm-gpio = <&gpio TEGRA_GPIO(V, 4) 0>; /* PV0 */
/* Only 2 lanes used on Porg */
nvidia,dsi-n-data-lanes = <2>;
};
};
sor1 {
/* Compared to Jetson-TX1's baseboard (P2597), HDMI TX
* lanes 0 and 2 have been swapped in Porg's baseboard
* (P3448) making it a straight lane mapping between
* SOR1 and the pad.
*/
nvidia,xbar-ctrl = <0 1 2 3 4>;
status = "okay";
hdmi-display {
status = "okay";
};
};
dpaux {
status = "okay";
};
dpaux1 {
status = "okay";
};
};
backlight {
compatible = "pwm-backlight";
status = "okay";
panel-a-wxga-8-0-bl {
status = "okay";
pwms = <&tegra_pwm 0 40161>;
};
};
pwm@7000a000 {
nvidia,no-clk-sleeping-in-ops;
};
pmc@7000e400 {
#nvidia,wake-cells = <3>;
nvidia,invert-interrupt;
nvidia,suspend-mode = <0>;
nvidia,cpu-pwr-good-time = <0>;
nvidia,cpu-pwr-off-time = <0>;
nvidia,core-pwr-good-time = <4587 3876>;
nvidia,core-pwr-off-time = <39065>;
nvidia,core-pwr-req-active-high;
nvidia,sys-clock-req-active-high;
iopad-defaults {
audio-hv-pads {
pins = "audio-hv";
nvidia,power-source-voltage = <TEGRA_IO_PAD_VOLTAGE_1800000UV>;
};
spi-hv-pads {
pins = "spi-hv";
nvidia,power-source-voltage = <TEGRA_IO_PAD_VOLTAGE_1800000UV>;
};
gpio-pads {
pins = "gpio";
nvidia,power-source-voltage = <TEGRA_IO_PAD_VOLTAGE_1800000UV>;
};
sdmmc-io-pads {
pins = "sdmmc1", "sdmmc3";
nvidia,enable-voltage-switching;
};
};
};
hdr40_spi1: spi@7000d400 { /* SPI 1 to 40 pin header */
status = "okay";
spi@0 {
compatible = "tegra-spidev";
reg = <0x0>;
spi-max-frequency = <33000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <7>;
};
};
spi@1 {
compatible = "tegra-spidev";
reg = <0x1>;
spi-max-frequency = <33000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <7>;
};
};
};
hdr40_spi2: spi@7000d600 { /* SPI 2 to 40 pin header */
status = "okay";
spi@0 {
compatible = "tegra-spidev";
reg = <0x0>;
spi-max-frequency = <33000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <6>;
};
};
spi@1 {
compatible = "tegra-spidev";
reg = <0x1>;
spi-max-frequency = <33000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <6>;
};
};
};
spi@7000d800 {
status = "disabled";
};
spi@7000da00 {
status = "disabled";
};
spi@70410000 {
status = "okay";
spi-max-frequency = <104000000>;
spiflash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "MX25U3235F";
reg = <0>;
spi-max-frequency = <104000000>;
controller-data {
nvidia,x1-len-limit = <4194304>;
nvidia,x1-bus-speed = <104000000>;
nvidia,x1-dymmy-cycle = <8>;
nvidia,ctrl-bus-clk-ratio = /bits/ 8 <0x01>;
};
};
};
sdhci@700b0600 { /* SDMMC4 for EMMC */
uhs-mask = <0x0>;
mmc-hs400-enhanced-strobe;
built-in;
power-off-rail;
status = "disabled";
bus-width = <8>;
non-removable;
/delete-property/ nvidia,enable-hs533-mode;
no-sdio;
no-sd;
pll_source = "pll_p", "pll_c4_out2";
max-clk-limit = <0xbebc200>;
};
sdhci@700b0400 {
status = "disabled";
/delete-property/ keep-power-in-suspend;
/delete-property/ non-removable;
mmc-ddr-1_8v;
mmc-ocr-mask = <3>;
uhs-mask = <0x0>;
tap-delay = <3>;
};
sdhci@700b0200 { /* SDMMC2 for Wifi */
uhs-mask = <0x8>;
power-off-rail;
force-non-removable-rescan;
status = "disabled";
};
sdhci@700b0000 { /* SDMMC1 for SD card */
default-drv-type = <1>;
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) 0>;
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
sd-uhs-sdr12;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
nvidia,cd-wakeup-capable;
nvidia,update-pinctrl-settings;
nvidia,pmc-wakeup = <&tegra_pmc PMC_WAKE_TYPE_GPIO 35
PMC_TRIGGER_TYPE_NONE>;
uhs-mask = <0xc>;
no-sdio;
no-mmc;
disable-wp;
status = "okay";
};
aconnect@702c0000 {
adma@702e2000 {
status = "okay";
};
ahub {
i2s@702d1000 {
status = "disabled";
};
i2s@702d1100 {
status = "disabled";
};
i2s@702d1200 {
regulator-supplies = "vdd-1v8-dmic";
vdd-1v8-dmic-supply = <&max77620_sd3>;
fsync-width = <15>;
status = "okay";
};
i2s@702d1300 {
regulator-supplies = "vddio-uart";
vddio-uart-supply = <&max77620_sd3>;
fsync-width = <15>;
status = "okay";
/*
* I2S4 on Jetson Nano uses the I2S4B pads
* and to use these pads bit 0 in the I2S_CYA
* register must be set.
*/
enable-cya;
};
i2s@702d1400 {
status = "disabled";
};
dmic@702d4000 {
regulator-supplies = "vdd-1v8-dmic";
vdd-1v8-dmic-supply = <&max77620_sd3>;
status = "okay";
};
dmic@702d4100 {
regulator-supplies = "vdd-1v8-dmic";
vdd-1v8-dmic-supply = <&max77620_sd3>;
status = "okay";
};
dmic@702d4200 {
status = "disabled";
};
};
};
hda@70030000 {
status = "okay";
};
tegra_sound: sound {
status = "okay";
compatible = "nvidia,tegra-audio-t210ref-mobile-rt565x";
nvidia,model = "tegra-snd-t210ref-mobile-rt565x";
clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA210_CLK_EXTERN1>;
clock-names = "pll_a", "pll_a_out0", "extern1";
assigned-clocks = <&tegra_car TEGRA210_CLK_EXTERN1>,
<&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA210_CLK_PLL_A>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
assigned-clock-rates = <12288000>, <49152000>, <368640000>;
nvidia,num-codec-link = <4>;
nvidia,audio-routing =
"x Headphone", "x OUT",
"x IN", "x Mic",
"y Headphone", "y OUT",
"y IN", "y Mic",
"a IN", "a Mic",
"b IN", "b Mic";
nvidia,xbar = <&tegra_axbar>;
mclk-fs = <256>;
hdr40_snd_link_i2s: i2s_dai_link1: nvidia,dai-link-1 {
link-name = "spdif-dit-0";
cpu-dai = <&tegra_i2s4>;
codec-dai = <&spdif_dit0>;
cpu-dai-name = "I2S4";
codec-dai-name = "dit-hifi";
format = "i2s";
bitclock-slave;
frame-slave;
bitclock-noninversion;
frame-noninversion;
bit-format = "s16_le";
srate = <48000>;
num-channel = <2>;
ignore_suspend;
name-prefix = "x";
status = "okay";
};
nvidia,dai-link-2 {
link-name = "spdif-dit-1";
cpu-dai = <&tegra_i2s3>;
codec-dai = <&spdif_dit1>;
cpu-dai-name = "I2S3";
codec-dai-name = "dit-hifi";
format = "i2s";
bitclock-slave;
frame-slave;
bitclock-noninversion;
frame-noninversion;
bit-format = "s16_le";
srate = <48000>;
num-channel = <2>;
ignore_suspend;
name-prefix = "y";
status = "okay";
};
nvidia,dai-link-3 {
link-name = "spdif-dit-2";
cpu-dai = <&tegra_dmic1>;
codec-dai = <&spdif_dit2>;
cpu-dai-name = "DMIC1";
codec-dai-name = "dit-hifi";
format = "i2s";
bit-format = "s16_le";
srate = <48000>;
ignore_suspend;
num-channel = <2>;
name-prefix = "a";
status = "okay";
};
nvidia,dai-link-4 {
link-name = "spdif-dit-3";
cpu-dai = <&tegra_dmic2>;
codec-dai = <&spdif_dit3>;
cpu-dai-name = "DMIC2";
codec-dai-name = "dit-hifi";
format = "i2s";
bit-format = "s16_le";
srate = <48000>;
ignore_suspend;
num-channel = <2>;
name-prefix = "b";
status = "okay";
};
};
extcon {
extcon@0 {
status = "disabled";
};
};
xusb_padctl@7009f000 {
status = "okay";
pads {
usb2 {
status = "okay";
lanes {
usb2-0 {
status = "okay";
nvidia,function = "xusb";
};
usb2-1 {
status = "okay";
nvidia,function = "xusb";
};
usb2-2 {
status = "okay";
nvidia,function = "xusb";
};
};
};
pcie {
status = "okay";
lanes {
pcie-0 {
status = "okay";
nvidia,function = "pcie-x1";
};
pcie-1 {
status = "okay";
nvidia,function = "pcie-x4";
};
pcie-2 {
status = "okay";
nvidia,function = "pcie-x4";
};
pcie-3 {
status = "okay";
nvidia,function = "pcie-x4";
};
pcie-4 {
status = "okay";
nvidia,function = "pcie-x4";
};
pcie-5 {
status = "okay";
nvidia,function = "xusb";
};
pcie-6 {
status = "okay";
nvidia,function = "xusb";
};
};
};
};
ports {
usb2-0 {
status = "okay";
mode = "otg";
nvidia,usb3-port-fake = <3>;
};
usb2-1 {
status = "okay";
mode = "host";
};
usb2-2 {
status = "okay";
mode = "host";
};
usb3-0 {
status = "okay";
nvidia,usb2-companion = <1>;
};
};
};
xusb@70090000 {
phys = <&{/xusb_padctl@7009f000/pads/usb2/lanes/usb2-0}>,
<&{/xusb_padctl@7009f000/pads/usb2/lanes/usb2-1}>,
<&{/xusb_padctl@7009f000/pads/usb2/lanes/usb2-2}>,
<&{/xusb_padctl@7009f000/pads/pcie/lanes/pcie-6}>;
phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
#extcon-cells = <1>;
nvidia,pmc-wakeup =
<&tegra_pmc
PMC_WAKE_TYPE_EVENT 39 PMC_TRIGGER_TYPE_HIGH>,
<&tegra_pmc
PMC_WAKE_TYPE_EVENT 40 PMC_TRIGGER_TYPE_HIGH>,
<&tegra_pmc
PMC_WAKE_TYPE_EVENT 41 PMC_TRIGGER_TYPE_HIGH>,
<&tegra_pmc
PMC_WAKE_TYPE_EVENT 42 PMC_TRIGGER_TYPE_HIGH>,
<&tegra_pmc
PMC_WAKE_TYPE_EVENT 44 PMC_TRIGGER_TYPE_HIGH>;
nvidia,boost_cpu_freq = <1200>;
status = "okay";
};
xudc@700d0000 {
phys = <&{/xusb_padctl@7009f000/pads/usb2/lanes/usb2-0}>;
phy-names = "usb2";
charger-detector = <&tegra_usb_cd>;
#extcon-cells = <1>;
status = "okay";
};
tegra_usb_cd: usb_cd {
reg = <0x0 0x7009f000 0x0 0x1000>;
phys = <&{/xusb_padctl@7009f000/pads/usb2/lanes/usb2-0}>;
phy-names = "otg-phy";
status = "disabled";
};
psy_extcon_xudc {
status = "disabled";
/delete-property/ dt-override-status-odm-data;
};
xotg {
status = "disabled";
#extcon-cells = <1>;
};
chosen {
nvidia,bootloader-vbus-enable=<0x1>;
nvidia,fastboot_without_usb;
nvidia,gpu-disable-power-saving;
board-has-eeprom;
firmware-blob-partition = "RP4";
verified-boot {
poweroff-on-red-state;
};
};
gpu-dvfs-rework {
status = "okay";
};
pwm_regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
cpu_ovr_reg: pwm-regulator@0 {
status = "okay";
reg = <0>;
compatible = "pwm-regulator";
pwms = <&tegra_pwm_dfll 0 2500>;
regulator-name = "vdd-cpu";
regulator-min-microvolt = <708000>;
regulator-max-microvolt = <1323400>;
regulator-always-on;
regulator-boot-on;
voltage-table =
<708000 0>, <727200 1>, <746400 2>,
<765600 3>, <784800 4>, <804000 5>,
<823200 6>, <842400 7>, <861600 8>,
<880800 9>, <900000 10>, <919200 11>,
<938400 12>, <957600 13>, <976800 14>,
<996000 15>, <1015200 16>, <1034400 17>,
<1053600 18>, <1072800 19>, <1092000 20>,
<1111200 21>, <1130400 22>, <1149600 23>,
<1168800 24>, <1188000 25>, <1207200 26>,
<1226400 27>, <1245600 28>, <1264800 29>,
<1284000 30>, <1303200 31>, <1322400 32>;
};
pwm-regulator@1 {
status = "okay";
reg = <1>;
compatible = "pwm-regulator";
pwms = <&tegra_pwm 1 8000>;
regulator-name = "vdd-gpu";
regulator-min-microvolt = <708000>;
regulator-max-microvolt = <1323400>;
regulator-init-microvolt = <1000000>;
regulator-n-voltages = <62>;
regulator-enable-ramp-delay = <2000>;
enable-gpio = <&max77620 6 0>;
regulator-settling-time-us = <160>;
};
};
soctherm@0x700E2000 {
throttle-cfgs {
throttle_oc1: oc1 {
nvidia,priority = <0>;
nvidia,polarity-active-low = <0>;
nvidia,count-threshold = <0>;
nvidia,alarm-filter = <0>;
nvidia,alarm-period = <0>;
nvidia,cpu-throt-percent = <0>;
nvidia,gpu-throt-level =
<TEGRA_SOCTHERM_THROT_LEVEL_NONE>;
};
throttle_oc3: oc3 {
nvidia,priority = <40>;
nvidia,polarity-active-low = <1>;
nvidia,count-threshold = <15>;
nvidia,alarm-filter = <5100000>;
nvidia,alarm-period = <0>;
nvidia,cpu-throt-percent = <75>;
nvidia,gpu-throt-level =
<TEGRA_SOCTHERM_THROT_LEVEL_MED>;
};
};
};
serial@70006000 { /* UART-A : UART1: Debug */
compatible = "nvidia,tegra210-uart", "nvidia,tegra114-hsuart", "nvidia,tegra20-uart";
console-port;
sqa-automation-port;
/delete-property/ resets;
/delete-property/ reset-names;
status = "okay";
};
serial@70006040 { /* UART-B : UART2 40 pin header */
compatible = "nvidia,tegra114-hsuart";
status = "okay";
};
serial@70006200 { /* UART-C : UART3 : M.2 Key E */
compatible = "nvidia,tegra114-hsuart";
dma-names = "tx";
nvidia,adjust-baud-rates = <921600 921600 100>;
status = "okay";
};
serial@70006300 { /* UART-D not used */
status = "disabled";
};
i2c@7000c700 { /* i2c4 */
status = "okay";
};
i2c@7000d000 {
clock-frequency = <1000000>;
};
dfll-max77621@70110000 {
i2c_dfll: dfll-max77621-integration {
i2c-fs-rate = <1000000>;
pmic-i2c-address = <0x36>;
pmic-i2c-voltage-register = <0x01>;
sel-conversion-slope = <1>;
};
dfll_max77621_parms: dfll-max77621-board-params {
sample-rate = <12500>;
fixed-output-forcing;
cf = <10>;
ci = <0>;
cg = <2>;
droop-cut-value = <0xf>;
droop-restore-ramp = <0x0>;
scale-out-ramp = <0x0>;
};
};
dfll_cap: dfll-cdev-cap {
compatible = "nvidia,tegra-dfll-cdev-action";
act-dev = <&tegra_clk_dfll>;
cdev-type = "DFLL-cap";
#cooling-cells = <2>; /* min followed by max */
};
dfll_floor: dfll-cdev-floor {
compatible = "nvidia,tegra-dfll-cdev-action";
act-dev = <&tegra_clk_dfll>;
cdev-type = "DFLL-floor";
#cooling-cells = <2>; /* min followed by max */
};
hdr40_i2c0: i2c@7000c000 {
tegra_nct72: temp-sensor@4c {
status = "disabled";
};
};
hdr40_i2c1: i2c@7000c400 { };
clock@70110000 {
status = "okay";
vdd-cpu-supply = <&cpu_ovr_reg>;
nvidia,dfll-max-freq-khz = <1479000>;
nvidia,pwm-to-pmic;
nvidia,init-uv = <1000000>;
nvidia,sample-rate = <25000>;
nvidia,droop-ctrl = <0x00000f00>;
nvidia,force-mode = <1>;
nvidia,cf = <6>;
nvidia,ci = <0>;
nvidia,cg = <2>;
nvidia,idle-override;
nvidia,one-shot-calibrate;
nvidia,pwm-period = <2500>; /* 2.5us */
pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
pinctrl-0 = <&dvfs_pwm_active_state>;
pinctrl-1 = <&dvfs_pwm_inactive_state>;
nvidia,align-offset-uv = <708000>;
nvidia,align-step-uv = <19200>;
};
dvfs {
compatible = "nvidia,tegra210-dvfs";
vdd-cpu-supply = <&cpu_ovr_reg>;
nvidia,gpu-max-freq-khz = <921600>;
};
rtc {
nvidia,pmc-wakeup = <&tegra_pmc PMC_WAKE_TYPE_EVENT 16
PMC_TRIGGER_TYPE_HIGH>;
};
nvpmodel {
status = "okay";
};
r8168 {
isolate-gpio = <&gpio TEGRA_GPIO(X, 3) 0>;
};
tegra_udrm: tegra_udrm {
compatible = "nvidia,tegra-udrm";
};
tegra_wdt: watchdog@60005100 {
dt-override-status-odm-data = <0x00010000 0x00010000>;
status = "disabled";
};
soft_wdt: soft_watchdog {
compatible = "softdog-platform";
dt-override-status-odm-data = <0x00030000 0x00000000>;
status = "okay";
};
gpio: gpio@6000d000 {
suspend_gpio: system-suspend-gpio {
status = "okay";
gpio-hog;
output-high;
gpio-suspend;
suspend-output-low;
gpios = <
TEGRA_GPIO(A, 6) 0
>;
};
};
leds {
compatible = "gpio-leds";
status = "disabled";
pwr {
gpios = <&gpio TEGRA_GPIO(I, 1) GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "system-throttle";
};
};
memory-controller@70019000 {
status = "okay";
};
mailbox@70098000 {
status = "okay";
};
memory@80000000 {
device_type = "memory";
reg = < 0x0 0x80000000 0x0 0x80000000 >;
};
pinmux@700008d4 {
dvfs_pwm_active_state: dvfs_pwm_active {
dvfs_pwm_pbb1 {
nvidia,pins = "dvfs_pwm_pbb1";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
};
dvfs_pwm_inactive_state: dvfs_pwm_inactive {
dvfs_pwm_pbb1 {
nvidia,pins = "dvfs_pwm_pbb1";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
};
};
pwm@70110000 {
pinctrl-0 = <&dvfs_pwm_active_state>;
pinctrl-1 = <&dvfs_pwm_inactive_state>;
pwm-regulator = <&cpu_ovr_reg>;
status = "okay";
};
nvdumper {
status = "disabled";
};
cpu_edp {
status = "okay";
nvidia,edp_limit = <0x61a8>;
};
gpu_edp {
status = "okay";
nvidia,edp_limit = <0x4e20>;
};
cpu_alert: cpu-throttle-alert {
status = "okay";
};
gpu_alert: gpu-throttle-alert {
status = "okay";
};
hot_surface_alert: hot-surface-alert {
compatible = "userspace-therm-alert";
cdev-type = "hot-surface-alert";
status = "okay";
#cooling-cells = <2>;
};
thermal-zones {
GPU-therm {
trips {
gpu_hot_surface_trip: gpu-hot-surface-trip {
temperature = <70000>;
hysteresis = <8000>;
type = "active";
};
};
cooling-maps {
gpu-hot-surface-map0 {
trip = <&gpu_hot_surface_trip>;
cooling-device = <&hot_surface_alert 1 1>;
};
};
};
PLL-therm {
trips {
pll_hot_surface_trip: pll-hot-surface-trip {
temperature = <70000>;
hysteresis = <8000>;
type = "active";
};
};
cooling-maps {
pll-hot-surface-map0 {
trip = <&pll_hot_surface_trip>;
cooling-device = <&hot_surface_alert 1 1>;
};
};
};
};
};
#if LINUX_VERSION >= 414
#include <tegra210-linux-4.14.dtsi>
#endif
Display settings in panel-a-wxga-8-0.dtsi
#include <dt-bindings/display/tegra-dc.h>
#include <dt-bindings/display/tegra-panel.h>
/ {
host1x {
dsi {
panel_a_wxga_8_0: panel-a-wxga-8-0 {
status = "disabled";
compatible = "a,wxga-8-0";
nvidia,dsi-instance = <DSI_INSTANCE_0>;
nvidia,dsi-n-data-lanes = <2>;
nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>;
nvidia,dsi-refresh-rate = <60>;
nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE>;
nvidia,dsi-video-clock-mode = <TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS>;
nvidia,dsi-video-burst-mode = <TEGRA_DSI_VIDEO_NONE_BURST_MODE>;
nvidia,dsi-virtual-channel = <TEGRA_DSI_VIRTUAL_CHANNEL_0>;
nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>;
nvidia,dsi-power-saving-suspend = <TEGRA_DSI_ENABLE>;
nvidia,dsi-ulpm-not-support = <TEGRA_DSI_ENABLE>;
/* Long Packet: <PACKETTYPE[u8] COMMANDID[u8] PAYLOADCOUNT[u16] ECC[u8] PAYLOAD[..] CHECKSUM[u16]> */
/* Short Packet: <PACKETTYPE[u8] COMMANDID[u8] DATA0[u8] DATA1[u8] ECC[u8]> */
/* For DSI packets each DT cell is interpreted as u8 not u32 */
nvidia,dsi-init-cmd = <TEGRA_DSI_DELAY_MS 160>,
<0x0 DSI_DCS_WRITE_0_PARAM DSI_DCS_EXIT_SLEEP_MODE 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 20>,
<0x0 DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_ON 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 20>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xFF 0x00 0x00 0x77 0x01 0x00 0x00 0x13 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xEF 0x08 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xFF 0x00 0x00 0x77 0x01 0x00 0x00 0x10 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xC0 0x00 0x00 0x3B 0x00 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xC1 0x00 0x00 0x10 0x0C 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xC2 0x00 0x00 0x07 0x0A 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xC7 0x00 0x00 0x00 0x00 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xCC 0x00 0x00 0x10 0x00 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xB0 0x00 0x00 0x05 0x12 0x98 0x0E 0x0F 0x07 0x07 0x09 0x09 0x23 0x05 0x52 0x0F 0x67 0x2C 0x11 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xB1 0x00 0x00 0x0B 0x11 0x97 0x0C 0x12 0x06 0x06 0x08 0x08 0x22 0x03 0x51 0x11 0x66 0x2B 0x0F 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xFF 0x00 0x00 0x77 0x01 0x00 0x00 0x11 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB0 0x5D 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB1 0x35 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB2 0x81 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB3 0x80 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB5 0x4E 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB7 0x85 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB8 0x20 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC1 0x78 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xC2 0x78 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xD0 0x88 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE0 0x00 0x00 0x00 0x00 0x02 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE1 0x00 0x00 0x06 0x30 0x08 0x30 0x05 0x30 0x07 0x30 0x00 0x33 0x33 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE2 0x00 0x00 0x11 0x11 0x33 0x33 0xF4 0x00 0x00 0x00 0xF4 0x00 0x00 0x00 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE3 0x00 0x00 0x00 0x00 0x11 0x11 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE4 0x00 0x00 0x44 0x44 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE5 0x00 0x00 0x0D 0xF5 0x30 0xF0 0x0F 0xF7 0x30 0xF0 0x09 0xF1 0x30 0xF0 0x0B 0xF3 0x30 0xF0 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE6 0x00 0x00 0x00 0x00 0x11 0x11 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE7 0x00 0x00 0x44 0x44 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE8 0x00 0x00 0x0C 0xF4 0x30 0xF0 0x0E 0xF6 0x30 0xF0 0x08 0xF0 0x30 0xF0 0x0A 0xF2 0x30 0xF0 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xE9 0x00 0x00 0x36 0x01 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xEB 0x00 0x00 0x00 0x01 0xE4 0xE4 0x44 0x88 0x40 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xED 0x00 0x00 0xFF 0x10 0xBF 0x76 0x54 0x2A 0xFC 0xFF 0xFF 0xCF 0xA2 0x45 0x67 0xFB 0x01 0xFF 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xEF 0x00 0x00 0x08 0x08 0x08 0x45 0x3F 0x54 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_LONG_WRITE 0xFF 0x00 0x00 0x77 0x01 0x00 0x00 0x00 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM 0x11 0x00 0x00>,
<TEGRA_DSI_DELAY_MS 120>, //ms
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x3A 0x66 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x36 0x10 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x35 0x00 0x00>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM 0x29 0x00 0x00>;
nvidia,dsi-n-init-cmd = <46>;
disp-default-out {
nvidia,out-type = <TEGRA_DC_OUT_DSI>;
nvidia,out-width = <107>;
nvidia,out-height = <172>;
nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
nvidia,out-parent-clk = "pll_d_out0";
nvidia,out-xres = <480>;
nvidia,out-yres = <480>;
};
display-timings {
480x480-32 {
clock-frequency = <5000000>;
hactive = <480>;
vactive = <480>;
hfront-porch = <140>;
hback-porch = <160>;
hsync-len = <8>;
vfront-porch = <20>;
vback-porch = <20>;
vsync-len = <8>;
nvidia,h-ref-to-sync = <1>;
nvidia,v-ref-to-sync = <1>;
};
};
cmu {
nvidia,cmu-csc = < 0x138 0x3ba 0x00d
0x3f5 0x120 0x3e6
0x3fe 0x3f8 0x0e9 >;
nvidia,cmu-lut2 = < 0 1 2 3 4 5 6 6
7 8 9 10 11 11 12 13
13 14 15 15 16 17 17 18
18 19 19 20 20 21 21 22
22 23 23 23 24 24 24 25
25 25 26 26 26 27 27 27
28 28 28 28 29 29 29 29
30 30 30 30 31 31 31 31
32 32 32 32 33 33 33 33
34 34 34 35 35 35 35 36
36 36 37 37 37 37 38 38
38 39 39 39 39 40 40 40
41 41 41 41 42 42 42 43
43 43 43 44 44 44 45 45
45 45 46 46 46 46 47 47
47 47 48 48 48 48 49 49
49 49 50 50 50 50 50 51
51 51 51 52 52 52 52 52
53 53 53 53 53 53 54 54
54 54 54 55 55 55 55 55
55 56 56 56 56 56 56 57
57 57 57 57 57 57 58 58
58 58 58 58 59 59 59 59
59 59 59 60 60 60 60 60
60 60 61 61 61 61 61 61
61 62 62 62 62 62 62 62
63 63 63 63 63 63 63 64
64 64 64 64 64 64 65 65
65 65 65 65 66 66 66 66
66 66 66 67 67 67 67 67
67 68 68 68 68 68 68 69
69 69 69 69 69 70 70 70
70 70 70 71 71 71 71 71
71 72 72 72 72 72 72 73
73 73 73 73 73 74 74 74
74 74 74 74 75 75 75 75
75 75 76 76 76 76 76 76
77 77 77 77 77 77 77 78
78 78 78 78 78 79 79 79
79 79 79 79 80 80 80 80
80 80 80 80 81 81 81 81
81 81 81 82 82 82 82 82
82 82 82 83 83 83 83 83
83 83 83 83 84 84 84 84
84 84 84 84 85 85 85 85
85 85 85 85 85 85 86 86
86 86 86 86 86 86 86 86
87 87 87 87 87 87 87 87
87 87 88 88 88 88 88 88
88 88 88 88 88 88 89 89
89 89 89 89 89 89 89 89
89 89 90 90 90 90 90 90
90 90 90 90 90 90 91 91
91 91 91 91 91 91 91 91
91 91 91 92 92 92 92 92
92 92 92 92 92 92 92 92
93 93 93 93 93 93 93 93
93 93 93 93 93 93 94 94
94 94 94 94 94 94 94 94
94 94 94 94 95 95 95 95
95 95 95 95 95 95 95 95
95 96 96 96 96 96 96 96
96 96 96 96 96 96 97 97
97 97 97 97 97 97 97 97
98 99 99 100 101 101 102 103
103 104 105 105 106 107 107 108
109 110 110 111 112 112 113 114
114 115 115 116 117 117 118 119
119 120 120 121 121 122 123 123
124 124 125 125 126 126 127 128
128 129 129 130 130 131 131 132
132 133 133 134 134 135 135 136
136 137 138 138 139 139 140 140
141 141 142 142 143 143 144 144
144 145 145 146 146 147 147 148
148 149 149 150 150 151 151 152
152 153 153 153 154 154 155 155
156 156 157 157 157 158 158 159
159 160 160 160 161 161 162 162
162 163 163 164 164 164 165 165
165 166 166 167 167 167 168 168
168 169 169 169 170 170 171 171
171 172 172 172 173 173 173 174
174 174 175 175 175 176 176 176
177 177 177 178 178 178 179 179
179 180 180 180 181 181 181 182
182 182 183 183 183 184 184 184
185 185 185 185 186 186 186 187
187 187 188 188 188 189 189 189
190 190 190 191 191 191 191 192
192 192 193 193 193 194 194 194
195 195 195 195 196 196 196 197
197 197 198 198 198 199 199 199
199 200 200 200 201 201 201 202
202 202 203 203 203 203 204 204
204 205 205 205 206 206 206 207
207 207 208 208 208 208 209 209
209 210 210 210 211 211 211 212
212 212 213 213 213 214 214 214
215 215 215 215 216 216 216 217
217 217 218 218 218 219 219 219
220 220 220 220 221 221 221 222
222 222 222 223 223 223 224 224
224 224 225 225 225 226 226 226
226 227 227 227 227 228 228 228
229 229 229 229 230 230 230 230
230 231 231 231 231 232 232 232
232 233 233 233 233 234 234 234
234 234 235 235 235 235 236 236
236 236 236 237 237 237 237 238
238 238 238 238 239 239 239 239
239 240 240 240 240 240 241 241
241 241 241 242 242 242 242 243
243 243 243 243 244 244 244 244
244 245 245 245 245 245 246 246
246 246 246 247 247 247 247 248
248 248 248 248 249 249 249 249
250 250 250 250 251 251 251 251
251 252 252 252 253 253 253 253
254 254 254 254 255 255 255 255 >;
};
};
};
};
backlight {
panel_a_wxga_8_0_bl: panel-a-wxga-8-0-bl {
status = "disabled";
compatible = "a,wxga-8-0-bl";
pwms = <&tegra_pwm 1 40161>;
max-brightness = <255>;
default-brightness = <224>;
bl-measured = < 0 0 1 2 3 4 5 6
7 8 9 9 10 11 12 13
13 14 15 16 17 17 18 19
20 21 22 22 23 24 25 26
27 27 28 29 30 31 32 32
33 34 35 36 37 37 38 39
40 41 42 42 43 44 45 46
47 48 48 49 50 51 52 53
54 55 56 57 57 58 59 60
61 62 63 64 65 66 67 68
69 70 71 71 72 73 74 75
76 77 77 78 79 80 81 82
83 84 85 87 88 89 90 91
92 93 94 95 96 97 98 99
100 101 102 103 104 105 106 107
108 109 110 111 112 113 115 116
117 118 119 120 121 122 123 124
125 126 127 128 129 130 131 132
133 134 135 136 137 138 139 141
142 143 144 146 147 148 149 151
152 153 154 155 156 157 158 158
159 160 161 162 163 165 166 167
168 169 170 171 172 173 174 176
177 178 179 180 182 183 184 185
186 187 188 189 190 191 192 194
195 196 197 198 199 200 201 202
203 204 205 206 207 208 209 210
211 212 213 214 215 216 217 219
220 221 222 224 225 226 227 229
230 231 232 233 234 235 236 238
239 240 241 242 243 244 245 246
247 248 249 250 251 252 253 255 >;
};
};
};
We implemented the display initialization according to the set of commands sent to us by the display manufacturer:
Write(Command , 0xFF);
Write(Parameter , 0x77);
Write(Parameter , 0x01);
Write(Parameter , 0x00);
Write(Parameter , 0x00);
Write(Parameter , 0x13);
Write(Command , 0xEF);
Write(Parameter , 0x08);
Write(Command , 0xFF);
Write(Parameter , 0x77);
Write(Parameter , 0x01);
Write(Parameter , 0x00);
Write(Parameter , 0x00);
Write(Parameter , 0x10);
Write(Command , 0xC0);
Write(Parameter , 0x3B);
Write(Parameter , 0x00);
Write(Command , 0xC1);
Write(Parameter , 0x10);
Write(Parameter , 0x0C);
Write(Command , 0xC2);
Write(Parameter , 0x07);
Write(Parameter , 0x0A);
Write(Command , 0xC7);
Write(Parameter , 0x00);
Write(Command , 0xCC);
Write(Parameter , 0x10);
Write(Command , 0xB0);
Write(Parameter , 0x05);
Write(Parameter , 0x12);
Write(Parameter , 0x98);
Write(Parameter , 0x0E);
Write(Parameter , 0x0F);
Write(Parameter , 0x07);
Write(Parameter , 0x07);
Write(Parameter , 0x09);
Write(Parameter , 0x09);
Write(Parameter , 0x23);
Write(Parameter , 0x05);
Write(Parameter , 0x52);
Write(Parameter , 0x0F);
Write(Parameter , 0x67);
Write(Parameter , 0x2C);
Write(Parameter , 0x11);
Write(Command , 0xB1);
Write(Parameter , 0x0B);
Write(Parameter , 0x11);
Write(Parameter , 0x97);
Write(Parameter , 0x0C);
Write(Parameter , 0x12);
Write(Parameter , 0x06);
Write(Parameter , 0x06);
Write(Parameter , 0x08);
Write(Parameter , 0x08);
Write(Parameter , 0x22);
Write(Parameter , 0x03);
Write(Parameter , 0x51);
Write(Parameter , 0x11);
Write(Parameter , 0x66);
Write(Parameter , 0x2B);
Write(Parameter , 0x0F);
Write(Command , 0xFF);
Write(Parameter , 0x77);
Write(Parameter , 0x01);
Write(Parameter , 0x00);
Write(Parameter , 0x00);
Write(Parameter , 0x11);
Write(Command , 0xB0);
Write(Parameter , 0x5D);
Write(Command , 0xB1);
Write(Parameter , 0x35);
Write(Command , 0xB2);
Write(Parameter , 0x81);
Write(Command , 0xB3);
Write(Parameter , 0x80);
Write(Command , 0xB5);
Write(Parameter , 0x4E);
Write(Command , 0xB7);
Write(Parameter , 0x85);
Write(Command , 0xB8);
Write(Parameter , 0x20);
Write(Command , 0xC1);
Write(Parameter , 0x78);
Write(Command , 0xC2);
Write(Parameter , 0x78);
Write(Command , 0xD0);
Write(Parameter , 0x88);
Write(Command , 0xE0);
Write(Parameter , 0x00);
Write(Parameter , 0x00);
Write(Parameter , 0x02);
Write(Command , 0xE1);
Write(Parameter , 0x06);
Write(Parameter , 0x30);
Write(Parameter , 0x08);
Write(Parameter , 0x30);
Write(Parameter , 0x05);
Write(Parameter , 0x30);
Write(Parameter , 0x07);
Write(Parameter , 0x30);
Write(Parameter , 0x00);
Write(Parameter , 0x33);
Write(Parameter , 0x33);
Write(Command , 0xE2);
Write(Parameter , 0x11);
Write(Parameter , 0x11);
Write(Parameter , 0x33);
Write(Parameter , 0x33);
Write(Parameter , 0xF4);
Write(Parameter , 0x00);
Write(Parameter , 0x00);
Write(Parameter , 0x00);
Write(Parameter , 0xF4);
Write(Parameter , 0x00);
Write(Parameter , 0x00);
Write(Parameter , 0x00);
Write(Command , 0xE3);
Write(Parameter , 0x00);
Write(Parameter , 0x00);
Write(Parameter , 0x11);
Write(Parameter , 0x11);
Write(Command , 0xE4);
Write(Parameter , 0x44);
Write(Parameter , 0x44);
Write(Command , 0xE5);
Write(Parameter , 0x0D);
Write(Parameter , 0xF5);
Write(Parameter , 0x30);
Write(Parameter , 0xF0);
Write(Parameter , 0x0F);
Write(Parameter , 0xF7);
Write(Parameter , 0x30);
Write(Parameter , 0xF0);
Write(Parameter , 0x09);
Write(Parameter , 0xF1);
Write(Parameter , 0x30);
Write(Parameter , 0xF0);
Write(Parameter , 0x0B);
Write(Parameter , 0xF3);
Write(Parameter , 0x30);
Write(Parameter , 0xF0);
Write(Command , 0xE6);
Write(Parameter , 0x00);
Write(Parameter , 0x00);
Write(Parameter , 0x11);
Write(Parameter , 0x11);
Write(Command , 0xE7);
Write(Parameter , 0x44);
Write(Parameter , 0x44);
Write(Command , 0xE8);
Write(Parameter , 0x0C);
Write(Parameter , 0xF4);
Write(Parameter , 0x30);
Write(Parameter , 0xF0);
Write(Parameter , 0x0E);
Write(Parameter , 0xF6);
Write(Parameter , 0x30);
Write(Parameter , 0xF0);
Write(Parameter , 0x08);
Write(Parameter , 0xF0);
Write(Parameter , 0x30);
Write(Parameter , 0xF0);
Write(Parameter , 0x0A);
Write(Parameter , 0xF2);
Write(Parameter , 0x30);
Write(Parameter , 0xF0);
Write(Command , 0xE9);
Write(Parameter , 0x36);
Write(Parameter , 0x01);
Write(Command , 0xEB);
Write(Parameter , 0x00);
Write(Parameter , 0x01);
Write(Parameter , 0xE4);
Write(Parameter , 0xE4);
Write(Parameter , 0x44);
Write(Parameter , 0x88);
Write(Parameter , 0x40);
Write(Command , 0xED);
Write(Parameter , 0xFF);
Write(Parameter , 0x10);
Write(Parameter , 0xBF);
Write(Parameter , 0x76);
Write(Parameter , 0x54);
Write(Parameter , 0x2A);
Write(Parameter , 0xFC);
Write(Parameter , 0xFF);
Write(Parameter , 0xFF);
Write(Parameter , 0xCF);
Write(Parameter , 0xA2);
Write(Parameter , 0x45);
Write(Parameter , 0x67);
Write(Parameter , 0xFB);
Write(Parameter , 0x01);
Write(Parameter , 0xFF);
Write(Command , 0xEF);
Write(Parameter , 0x08);
Write(Parameter , 0x08);
Write(Parameter , 0x08);
Write(Parameter , 0x45);
Write(Parameter , 0x3F);
Write(Parameter , 0x54);
Write(Command , 0xFF);
Write(Parameter , 0x77);
Write(Parameter , 0x01);
Write(Parameter , 0x00);
Write(Parameter , 0x00);
Write(Parameter , 0x00);
Write(Command , 0x11);
Delay(120); //ms
Write(Command , 0x3A);
Write(Parameter , 0x66);
Write(Command , 0x36);
Write(Parameter , 0x10);
Write(Command , 0x35);
Write(Parameter , 0x00);
Write(Command , 0x29);
They also sent a datasheet and a description of the settings and timings:
Z28008-P24-ZC1.pdf (919.2 KB)
Could you help us to solve this problem? "
Also, regarding your last post, in the files of this post you can see that the RESET C4 port is configured as a regular pin and the pvm port is configured for backlight. These are two different pins.
Also, I checked the board-panel.c and it implements the call of these ports:
int tegra_panel_gpio_get_dt(const char *comp_str,
struct tegra_panel_of *panel)
{
int cnt = 0;
char *label = NULL;
int err = 0;
struct device_node *node =
of_find_compatible_node(NULL, NULL, comp_str);
/*
* If gpios are already populated, just return.
*/
if (panel->panel_gpio_populated)
return 0;
if (!node) {
pr_info("%s panel dt support not available\n", comp_str);
err = -ENOENT;
goto fail;
}
panel->panel_gpio[TEGRA_GPIO_RESET] =
of_get_named_gpio(node, "nvidia,panel-rst-gpio", 0);
panel->panel_gpio[TEGRA_GPIO_PANEL_EN] =
of_get_named_gpio(node, "nvidia,panel-en-gpio", 0);
panel->panel_gpio[TEGRA_GPIO_PANEL_EN_1] =
of_get_named_gpio(node, "nvidia,panel-en-1-gpio", 0);
panel->panel_gpio[TEGRA_GPIO_BL_ENABLE] =
of_get_named_gpio(node, "nvidia,panel-bl-en-gpio", 0);
panel->panel_gpio[TEGRA_GPIO_PWM] =
of_get_named_gpio(node, "nvidia,panel-bl-pwm-gpio", 0);
panel->panel_gpio[TEGRA_GPIO_BRIDGE_EN_0] =
of_get_named_gpio(node, "nvidia,panel-bridge-en-0-gpio", 0);
panel->panel_gpio[TEGRA_GPIO_BRIDGE_EN_1] =
of_get_named_gpio(node, "nvidia,panel-bridge-en-1-gpio", 0);
panel->panel_gpio[TEGRA_GPIO_BRIDGE_REFCLK_EN] =
of_get_named_gpio(node,
"nvidia,panel-bridge-refclk-en-gpio", 0);
for (cnt = 0; cnt < TEGRA_N_GPIO_PANEL; cnt++) {
if (gpio_is_valid(panel->panel_gpio[cnt])) {
switch (cnt) {
case TEGRA_GPIO_RESET:
label = "tegra-panel-reset";
break;
case TEGRA_GPIO_PANEL_EN:
label = "tegra-panel-en";
break;
case TEGRA_GPIO_PANEL_EN_1:
label = "tegra-panel-en-1";
break;
case TEGRA_GPIO_BL_ENABLE:
label = "tegra-panel-bl-enable";
break;
case TEGRA_GPIO_PWM:
label = "tegra-panel-pwm";
break;
case TEGRA_GPIO_BRIDGE_EN_0:
label = "tegra-panel-bridge-en-0";
break;
case TEGRA_GPIO_BRIDGE_EN_1:
label = "tegra-panel-bridge-en-1";
break;
case TEGRA_GPIO_BRIDGE_REFCLK_EN:
label = "tegra-panel-bridge-refclk-en";
break;
default:
pr_err("tegra panel no gpio entry\n");
}
if (label) {
err = gpio_request(panel->panel_gpio[cnt],
label);
if (err < 0) {
pr_err("gpio request failed for %s\n",
label);
goto fail;
}
label = NULL;
}
}
}
if (gpio_is_valid(panel->panel_gpio[TEGRA_GPIO_PWM]))
gpio_free(panel->panel_gpio[TEGRA_GPIO_PWM]);
panel->panel_gpio_populated = true;
fail:
of_node_put(node);
return err;
}
Also, implemented the call of the “a,wxga-8-0-bl”
static bool tegra_available_pwm_bl_ops_register(struct device *dev)
{
struct device_node *np_bl = NULL;
struct device_node *np_parent = NULL;
const char *pn_compat = NULL;
bool ret = false;
np_parent = of_find_node_by_path("/backlight");
if (np_parent) {
for_each_available_child_of_node(np_parent, np_bl) {
if (np_bl)
break;
}
}
if (!np_bl) {
pr_info("no avaiable target backlight node\n");
goto end;
}
pn_compat = of_get_property(np_bl, "compatible", NULL);
if (!pn_compat) {
WARN(1, "No compatible prop in backlight node\n");
goto end;
}
if (of_device_is_compatible(np_bl, "p,wuxga-10-1-bl")) {
dev_set_drvdata(dev, dsi_p_wuxga_10_1_ops.pwm_bl_ops);
} else if (of_device_is_compatible(np_bl, "lg,wxga-7-bl")) {
dev_set_drvdata(dev, dsi_lgd_wxga_7_0_ops.pwm_bl_ops);
} else if (of_device_is_compatible(np_bl, "s,wqxga-10-1-bl")) {
dev_set_drvdata(dev, dsi_s_wqxga_10_1_ops.pwm_bl_ops);
} else if (of_device_is_compatible(np_bl, "c,wxga-14-0-bl")) {
dev_set_drvdata(dev, lvds_c_1366_14_ops.pwm_bl_ops);
} else if (of_device_is_compatible(np_bl, "a,1080p-14-0-bl")) {
dev_set_drvdata(dev, dsi_a_1080p_14_0_ops.pwm_bl_ops);
} else if (of_device_is_compatible(np_bl, "j,1440-810-5-8-bl")) {
dev_set_drvdata(dev, dsi_j_1440_810_5_8_ops.pwm_bl_ops);
} else if (of_device_is_compatible(np_bl, "s,wuxga-7-0-bl")) {
dev_set_drvdata(dev, dsi_s_wuxga_7_0_ops.pwm_bl_ops);
} else if (of_device_is_compatible(np_bl, "s,wuxga-8-0-bl")) {
dev_set_drvdata(dev, dsi_s_wuxga_8_0_ops.pwm_bl_ops);
} else if (of_device_is_compatible(np_bl, "a,wuxga-8-0-bl")) {
dev_set_drvdata(dev, dsi_a_1200_1920_8_0_ops.pwm_bl_ops);
} else if (of_device_is_compatible(np_bl, "a,wxga-8-0-bl")) {
dev_set_drvdata(dev, dsi_a_1200_800_8_0_ops.pwm_bl_ops);
} else if (of_device_is_compatible(np_bl, "i-edp,1080p-11-6-bl")) {
dev_set_drvdata(dev, edp_i_1080p_11_6_ops.pwm_bl_ops);
} else if (of_device_is_compatible(np_bl, "a-edp,1080p-14-0-bl")) {
dev_set_drvdata(dev, edp_a_1080p_14_0_ops.pwm_bl_ops);
} else if (of_device_is_compatible(np_bl, "j,720p-5-0-bl")) {
dev_set_drvdata(dev, dsi_j_720p_5_ops.pwm_bl_ops);
} else if (of_device_is_compatible(np_bl, "l,720p-5-0-bl")) {
dev_set_drvdata(dev, dsi_l_720p_5_loki_ops.pwm_bl_ops);
} else if (of_device_is_compatible(np_bl, "s-edp,uhdtv-15-6-bl")) {
dev_set_drvdata(dev, edp_s_uhdtv_15_6_ops.pwm_bl_ops);
} else if (of_device_is_compatible(np_bl, "p-edp,3000-2000-13-5-bl")) {
dev_set_drvdata(dev, edp_p_3000_2000_13_5_ops.pwm_bl_ops);
} else if (of_device_is_compatible(np_bl, "o,720-1280-6-0-bl")) {
dev_set_drvdata(dev, dsi_o_720p_6_0_ops.pwm_bl_ops);
} else if (of_device_is_compatible(np_bl, "o,720-1280-6-0-01-bl")) {
dev_set_drvdata(dev, dsi_o_720p_6_0_ops.pwm_bl_ops);
} else if (of_device_is_compatible(np_bl, "dsi,1080p-bl")) {
} else if (of_device_is_compatible(np_bl, "dsi,2820x720-bl")) {
} else if (of_device_is_compatible(np_bl, "dsi,25x16-bl")) {
} else {
pr_info("invalid compatible for backlight node\n");
goto end;
}
ret = true;
end:
of_node_put(np_parent);
of_node_put(np_bl);
return ret;
}
Menuconfig settings:
Why does the display driver not pull the pin reset?
Also, just as you can see from the config menu, the “Generic PWM Backlight Driver” is enabled, and in theory, it should be responsible for setting the backlight and controlling the pvm, right? Or do we still need to write your own backlight driver?
Hi,
Just some debug tips and concept
-
I won’t be able to solve your problem by just reading your comment or spec. It is you that need to trace code and resolve the problem.
The reason of DSI is not widely supported is because this thing can be varied case by case. You may need to consult with the panel vendor too. -
Please forget about the pwm driver first. That thing really does not matter here.
You can manually enable pwm by the node and measure the signal. If the pwm signal is correct, then backlight should be ON. In this situation, focus on the DSI signa first. -
After turning on the power, we saw on the oscilloscope that the reset pin became a logical one and there were no switching of this pin."
So what is the expected value you want to get on the reset pin?
Also, have you ever checked the driver of panel-a-wxga-8-0?
The rst pin should be enabled there.
Yes, sure. nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>;
My question is how does the nvidia panel driver control the reset pin? I saw in the file board-panel.c there is a call to this pin from device three, but I did not see the implementation of the logic of this pin. Is this implemented somewhere else or do I need to implement it myself?
I also have a question about setting the frequency. This parameter is implemented in setting the tegradc nvidia, emc-clk-rate = <300000000>; Also, in the device tree of the panel in display-timings there is a parameter clock-frequency = <25000000>; Which of these settings will give me clocking on dsi?
As I already mentioned here:
The path of this file is kernel/nvidia/drivers/video/tegra/dc/panel/.
It is not only “board-panel.c”. Every panel file in this directory is mapping to its own device tree property and get parsed in of_dc.c Check of_dc.c and it will tell you which ops are mapping to “panel-a-wxga-8-0”
The display-timings decides the clock on DSI.
Thank you a lot for your response, it is very important information for me!
Also, in the dmesg logs I see that the frequency of the DSI HS is 150000.
However, I set the frequency to 25000000, which is equal to the nominal pclk. But I don’t see 25MHz on the dsi lines.
What else is needed to set the dsi frequency?
Do I need to enable something in the menuconfig to activate the kernel/nvidia/drivers/video/tegra/dc/panel/ driver? I don’t understand whether this driver is enabled or disabled. And if it is disabled, then where to enable it without enabling DRM in the menuconfig.
Hi,
It does not matter with menuconfig. And it does not matter with DRM.
dc.c driver is the entry point of all these things… Your “tegradc tegradc.1” is printed from it.
When during probe function, tegradc_probe shall register the the driver mentioned in kernel/nvidia/drivers/video/tegra/dc/panel/ by recognizing the device tree “compatible” string.
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