Our company bought few Jetson TX2 dev kit and System hibernation is a must feature for us and we are at its planning stage.
I could find, arm64 hibernation patches in mailing lists. I am trying to port them to TX2.
But I feel some statements in TRM are not giving a confidence for my planning stage.
After reading Parker’s TRM, I understood the following.
1] Parker SoC uses certain power management firmwares(bpmp.bin).
2] It has some AON cluster which does some Power management stuffs for Parker.
3] BPMP, a dedicated boot and power management core is present on which bpmp.bin is running.
4] There is a Power management controller (PMC) which does some system context save before LP0 entry.
5] PMC also assert reset signal to all modules in the SoC during LP0 exit.
6] Along with this ARMv PSCI is also present.
I think, system is giving a secure call to PSCI for suspend-to-mem. And then PSCI, PMC, and PM firmware plays some crucial role. This role is unknown to me.
7] Also some pads states are retained even during LP0(suspend-to-ram or deep sleep state) state.
8] Also in the kernel platform code I could not find much saving and restoring of context of different IPs.
9] I could not find who is saving and restoring CCPLEX’s GIC context.
Also there are other GIC present for other engine cores as well.
8] PMIC is connected to BPMP’s i2c contoller.
This means while wakeup BPMP fw does something on PMIC configuration. Is it?
9] From L4T 27.1 linux kernel soruce, I could not understand who is currently restoring PLLs, other CAR registers, and power to different IPs in SoC during a suspend-to-mem(entry and exit from LP0).
10] Separate GPMC is present for saving context of GPU. These saving are done on that IP’s internal RAM and not to external DRAM.
11] Microcode carveout reservation of 128MB is present in DRAM for Denver CPUs and it cannot be accessed by CCPLEX.
I think system hibernation has to anyways save all such information to Disk and restore them while resuming. And this I can do it from linux kernel only as other parts are black box for me.
As I could not get much information about all these important save/restore of context of different IPs in SoC from nvidia’s linux 4.4, and crucial role played by PM firmwares, I am little worried to move forward as I know arm64 hibernation patches along will not help me.
Any suggestion from Nvidia would be really help full in this situation.
I am using L4T 27.1 for my BSP work.