Looking at the SoC technical reference manual (v1.2), it lists C0 through C4 as available PCIe controllers in UPHY0, but the design guide does not reference C2 or C3 at all…
I found this topic that states C2 is not supported, but does not provide a reason:
Is there more documentation that better defines the constraints for allocating high-speed lanes to external interfaces?
The reason for no support is simple.
Not every functionality there has gone through our validation.
TRM is just for hardware capability for this SoC. What you told is correct but we didn’t implement a software driver to do what you want there.
The SoC capability does not mean you can do that on the module either.
For example, Orin Nano is same SoC as Orin AGX, but the pinout is different. Some pins are not even existed on Orin Nano SoC.
In such case, this info from TRM does not mean you can use that on Orin Nano.
Also, You already refer to the better document. The design guide is the better document. The content inside of it is what we already validated.
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