How another CPU communicate with Xavier through PCIE? (Solved)

Host could be running any OS

And under windows device manager what will it show as the device ?

Is there a way to flash the xavier as endpoint through the Jetpack SDK Manager?

What does it mean ‘compile tegra-pcie-ep-mem.c on host PC’ how exactly do I do that is there a video or documentation?

And under windows device manager what will it show as the device ?
If your question is about the class of the device, then, it is shown as a device of type ‘Memory Controller’ class

Is there a way to flash the xavier as endpoint through the Jetpack SDK Manager?
Please refer to https://devtalk.nvidia.com/default/topic/1048582/jetson-agx-xavier/the-problem-about-xavier-pcie-endpoint-mode/ post

What does it mean ‘compile tegra-pcie-ep-mem.c on host PC’ how exactly do I do that is there a video or documentation?
This is a Linux device driver file for Xavier PCIe endpoint mode controller. Copy it to any Host OS running Linux OS and compile it like any other Linux device driver file.
We don’t have windows version of the driver (But, one can develop the windows version of the driver looking at tegra-pcie-ep-mem.c file)

Where are there tegra-pcie-ep-mem.c and pcie-tegra-dw-ep.c files located?

Please download our kernel source and you will see it.

Hi Wayne,

I was unable to find it in the kernel source, what directory is it under?

kernel/nvidia$ find -iname “pcie-tegra-dw-ep.c”
./drivers/pci/ep/pcie-tegra-dw-ep.c

No idea what is your problem now.

Please refer to

https://devtalk.nvidia.com/default/topic/1050616/jetson-agx-xavier/the-bandwidth-of-of-virtual-ethernet-over-pcie-between-two-xaviers-is-low/1

What are some use cases for PCIe End Point? When would you need/want Xavier as endpoint vs root complex?
If all you have access to is the RAM wouldn’t you be losing out on most of the functionality DLA, GPU, CPU of Xavier? How are people meant to be using this?

Hi keithdm,

Please open a new topic for your issue. Thanks