How can fix “csi clock settle time: 13, cil settle time: 10” at TX1 R28.2
maybe I need set the csi clock settle time?
How can I fix this?
[ 64.452219] imx274 6-001a: imx274_power_off: power off
[ 64.457537] imx274 6-001a: imx274_power_off reset_gpio to 0
[ 64.463593] imx274 6-001a: imx274_power_off mclk disable
[ 77.941871] imx274 6-001a: imx274_power_on: power on
[ 77.946858] imx274 6-001a: imx274_power_on mclk enable
[ 78.052328] imx274 6-001a: imx274_power_on reset_gpio to 0
[ 78.158106] imx274 6-001a: imx274_power_on reset_gpio to 1
[ 78.290672] vi 54080000.vi: Calibrate csi port 0
[ 78.297571] imx274 6-001a: imx274_power_off: power off
[ 78.306693] imx274 6-001a: imx274_power_off reset_gpio to 0
[ 78.312659] imx274 6-001a: imx274_power_off mclk disable
[ 78.318297] imx274 6-001a: imx274_power_on: power on
[ 78.323362] imx274 6-001a: imx274_power_on mclk enable
[ 78.428918] imx274 6-001a: imx274_power_on reset_gpio to 0
[ 78.534642] imx274 6-001a: imx274_power_on reset_gpio to 1
[ 78.667175] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 78.673614] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000000
[ 78.679377] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000000
[ 78.685230] vi 54080000.vi: cil_settingtime is pulled from device
[ 78.691563] vi 54080000.vi: cil_settingtime was autocalculated
[ 78.697482] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 78.704517] vi 54080000.vi: cil_settingtime is pulled from device
[ 78.714570] vi 54080000.vi: cil_settingtime was autocalculated
[ 78.720421] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 83.809671] imx274 6-001a: imx274_power_off: power off
[ 83.814833] imx274 6-001a: imx274_power_off reset_gpio to 0
[ 83.821105] imx274 6-001a: imx274_power_off mclk disable