How could I debug SPE fw demo ?

Hello all,

spe-fw has been updated successfully. But I dont ever debugging any IDE or executable file? Accually, I want to see output for my code.
You know. For debugging you are writing printf or etc. in order to see output…
How could I do that ?

Hello, hamzaygrtc:
Please take a look at doc/, which provide some information about debug port.
In TX2, UARTG is used by SPE firmware as debug port.
In Jetson TX2, you may have to fly wires for UARTG tx/rx and check messages printed by SPE firmware.


# For Jetson TX2 #

There are 2 UART ports in AON cluster for Jetson TX2:
- UARTC (base address: 0x0c280000)
- UARTG (base address: 0x0c290000)

@note UARTG is also used by SPE firmware debug message output in Jetson TX2.
It's NOT recommended to use UARTG unless the end users know exactly how it

In order to access AON UART from the Cortex-R5 SPE/AON; the UART SCR and
Pinmux settings need to be updated to enable access to it as described in below

1. Check UART SCR settings to make sure that SPE can access the module in the
file mobile_scr.cfg:

       scr.1862.2 = 0x38001414; # CLK_RST_CONTROLLER_AON_SCR_UARTC_0

2. Check the PADCTL register for the UART pins to make sure that they work in
   UART mode. `tegra186-mb1-bct-pinmux-quill-p3310-1000-a00.cfg`:

       pinmux.0x0c302020 = 0x00000400; # uart3_tx_pw2: uartc
       pinmux.0x0c302018 = 0x00000458; # uart3_rx_pw3: uartc

3. Flash the entire board to ensure that the SCR and pinmux settings are
flashed on the board.

4. Check kernel device tree to make sure that kernel will not initialize
UART module under test against the settings in R5 firmware.
For example, in R28.2.1, UARTC is configured in DTS as following by:
    serial@c280000 {
            compatible = "nvidia,tegra186-hsuart";
            status = "okay";
Then kernel will re-initialize UARTC by high-speed mode, which will be
conflicted with R5 firmware sample code. Please comment out this part of
code and upgrade the kernel DTB.

After the UART test task runs, it will continuously output following messages
to desired UART port:
Message from SPE R5 UART
And also print received characters to debug port.

5. A simple way to test UARTC function in Jetson TX2 board.
5.1 Follow above steps from 1 to 4 and power up the device.
5.2 Use a wire to connect UARTC TX and Rx (in Jetson TX2 carrier board, they
are pin 5 and 4 in J17), then the following message will output from
SPE firmware debug UART port, i.e. UARTG:
Message from SPE R5 UART

Hello jachen ,

  • I couldn’t find mobile_scr.cfg and tegra186-mb1-bct-pinmux-quill-p3310-1000-a00.cfg files.

  • I have TTL USB cable. what is the difference UARTC or UARTG. I could’t find anywhere. Which pins I will connect on the board ?

Hello, hamzaygrtc:
You can find those files in flash directory:

building-pc:~/Work/jetson_customer/32.2/Linux_for_Tegra$ ls -l ./bootloader/t186ref/BCT/mobile_scr.cfg ./bootloader/t186ref/BCT/tegra186-mb1-bct-pinmux-quill-p3310-1000-a00.cfg
-rw-rw-rw- 1 root root 160075 7月  17 08:25 ./bootloader/t186ref/BCT/mobile_scr.cfg
-rw-rw-rw- 1 root root  27356 7月  17 08:25 ./bootloader/t186ref/BCT/tegra186-mb1-bct-pinmux-quill-p3310-1000-a00.cfg

UARTC and UARTG are different UART ports for TX2. You can cross-check with TX2 TRM and carrier board schematic for details.