Each TC (tensor core) SASS instruction will require a TC unit to operate on, per warp. The number of TC units per SM (and their throughput) vary by GPU architecture.
So when an HMMA instruction is issued warp-wide, it will occupy a TC unit for that issue slot/cycle. On subsequent cycles, another HMMA instruction can be issued to that unit, whether from the same warp in the case of independent instructions, or from a different warp assigned to that SM, based on the distribution of warps to warp schedulers/subpartitions.
Some per-architecture accounting can be found here.
To a first order approximation, the throughput of a particular op will be the number of flops/op for that instruction, divided by the number of flops per clock for a particular architecture TC unit, multiplied by the total number of TC units in the GPU (multiplied by the GPU clock rate).