How PCIe C5 root complex is enabled in device tree?

Autonomous Machines Jetson & Embedded Systems Jetson AGX Xavier
#1

In “tegra194-p2888-p2822-pcie-plugin-manager.dtsi”, we can find the code below:

fragment-pcie-c5-rp {
		odm-anded-override;
		odm-data = "disable-pcie-c5-endpoint", "enable-nvhs-uphy-pcie-c5";
		override@0 {
			target = <&{/pcie@141a0000}>;
			_overlay_ {
				status = "okay";
			};
		};
		override@1 {
			target = <&{/pcie_ep@141a0000}>;
			_overlay_ {
				status = "disabled";
			};
		};
		override@2 {
			target = <&{/gpio@c2f0000/pex-refclk-sel-low}>;
			_overlay_ {
				status = "okay";
			};
		};
	};

	fragment-pcie-c5-ep {
		odm-anded-override;
		odm-data = "enable-pcie-c5-endpoint", "enable-nvhs-uphy-pcie-c5";
		override@0 {
			target = <&{/pcie@141a0000}>;
			_overlay_ {
				status = "disabled";
			};
		};
		override@1 {
			target = <&{/pcie_ep@141a0000}>;
			_overlay_ {
				status = "okay";
			};
		};
		override@2 {
			target = <&{/gpio@c2f0000/pex-refclk-sel-high}>;
			_overlay_ {
				status = "okay";
			};
		};
	};

I am not very familiar with device tree. According to my understanding, “fragment-pcie-c5-rp” and “fragment-pcie-c5-ep” have conflict with each other. How these two fragments exist at the same time and make root-complex mode enabled?

Thanks.

#2

There is something called ODM data which is passed while flashing and the ODM data decides many things of which one is the operation of C5 controller for RootPort or EndPoint. Default ODM data make C5 controller operate in RootPort mode of operation. You are right both the nodes you mentioned are mutually exclusive and only one gets enabled (based on ODM data)

#3

When you flash the system using flash.sh, the ODMDATA value is set. One bit there (bit 12) determines whether PCIe controller C5 is configured as a root port or and endpoint. So, if your existing p2972-0000.conf.common says:

ODMDATA=0x9190000

… then change it to the following to set endpoint mode instead:

ODMDATA=0x9191000