How specify XUSB register address

I try to access T_XUSB_XHCI_OP_PORTPMSCHS register.
But the description of TRM register address is “offset: 0x424 - 0x514”.
・T_XUSB_XHCI_OP_PORTPMSCHS : 4byte
・TRM description offset range : 0xf0 byte
The target register length and TRM description length are not match.
How do I specify the address?

TRM : TECHNICAL REFERENCE MANUAL NVIDIA Tegra X1 Mobile Processor v1.1p

Hi yamamoto, please share why you need to configure the register. Any functionality is not implemented in current xhci driver?

Hi DaneLLL, thanks reply.

I want to execute USB host’s electrical compliance test(TEST_SE0_NAK,TEST_J,TEST_K and TEST_PACKET).
I read the forum *1 and ran the script" tegra_hc_test_v3_static".
sudo ./tegra_hc_test_v3_static -x 3

As a result , I was able to observed the waveform of the TEST_PACKET.
But,I have not been able to observe other tests(TEST_SE0_NAK,TEST_J and TEST_K) waveform yet.
So, I want to output the waveform of the other tests by changing T_XUSB_XHCI_OP_PORTPMSCHS register.

*1 : https://devtalk.nvidia.com/default/topic/934176/jetson-tk1/usb-2-0-high-speed-device-sq-testing-on-jetson-tk1/post/4872096/#4872096

Hi,
So you would like to run usb2.0 compliance test on TX1? Do you run it on devkit or your custom board?

Yes, USB2.0 compliance test on TX1.
I am going to run custom board.

My custom board has two USB3.0 TYPE A ports.
TX1’s pin A38/39 and B42/43 are connected to each USB3.0 port.

I want to run compliance test for each port.

Hi yasuhiro,
tegra_hc_test_v3_static only supports TEST_PACKET. For others, please overwrite test_selector in xhci-hub.c

/* XHCI 4.19.6 */
		case USB_PORT_FEAT_TEST:
			/*
			 * Test modes are only supported
			 * on USB 2.0 protocol Root Hub ports,
			 */
			if (hcd->speed != HCD_USB2)
				goto error;

			if (!test_selector || test_selector > 5)
				goto error;

			if (xhci_halt(xhci))
				goto error;

			/* Start test mode in PORTPMSC */
			temp = xhci_readl(xhci, port_array[wIndex] + 1);
			temp = xhci_port_state_to_neutral(temp);
			temp |= test_selector << 28;
			xhci_writel(xhci, temp, port_array[wIndex] + 1);
			break;

TEST_SE0_NAK 0011b
TEST_J 0001b
TEST_K 0010b

Hi DaneLL
Thank you for reply.

I modified the source code according to your advice.
But I haven’t observed compliance test’s waveform yet.
I tried to run same test with Jetson TX1 Developer Kit[http://www.nvidia.com/object/embedded-systems-dev-kits-modules.html] but it was the same result.

My test step is
[In Target board is Jetson TX1 Developer Kit]

  1. kernel driver build and run flash.sh to TX1’s eMMC.
  2. sudo ./tegra_hc_test_v3_static -x 3
  3. Check register value after readback. * see following my code.
  4. Observe USB port D+ and D- with oscilloscope.

What should I do?

My custom code is here.

xhci-hub.c
function : xhci_hub_control

/* XHCI 4.19.6 */
		case USB_PORT_FEAT_TEST:
			/*
			 * Test modes are only supported
			 * on USB 2.0 protocol Root Hub ports,
			 */
			if (hcd->speed != HCD_USB2)
				goto error;

			if (!test_selector || test_selector > 5)
				goto error;

			if (xhci_halt(xhci))
				goto error;

			/* Start test mode in PORTPMSC */
			temp = xhci_readl(xhci, port_array[wIndex] + 1);
			temp = xhci_port_state_to_neutral(temp);

                        test_selector = 0x01; // TEST_J.

			temp |= test_selector << 28;
                        // Check temp value.
			printk("write register [%x] \n", temp);
			xhci_writel(xhci, temp, port_array[wIndex] + 1);
                        // Read back register.
 			temp = xhci_readl(xhci, port_array[wIndex] + 1);
			printk("read register [%x] \n",temp);
			break;

Hi yasuhiro,
Does it work for TEST_SE0_NAK, TEST_K?

Or it only works for TEST_PACKET?

Of course, I tried run test TEST_SE0_NAK and TEST_K too.
All failed. Only work TEST_PACKET.

Hi yasuhiro,
Please check if you can get TEST_J with the binary attached.

Usage: ./usb_enable_port_test_j <-d sysfs-device-name> <-p port>
Example: "./usb_enable_port_test_j -d usb1 -p 2" to enable sending
        test packets for port 2 of "usb1" roothub.

usb_enable_port_test_j.zip (5.72 KB)

Hi DaneLLL.

Thank you for your response and script.

I tried run compliance test(TEST_J) with your script.
But test was failed. I wasn’t able to observe TEST_J’s waveform.

So I have two questions.

Question:

  1. Is your script's control sequence correct? I compared logs between your script and tegra_hc_port_test_v3_static by code inserted printk statement(see following code diff). I think the "ClearPortFeature USB_PORT_FEAT_POWER" sequence is lacked in your script from printk's kernel log result. PORTSC_PLS register was 4 in tegra_hc_port_test_v3_static and 5 in your script.
  2. Is xhci-hub.c's control correct? I guess that xhci-hub.c's control target is Intel XHCI controller. I googled "XHCI HOST CONTROLLER" I found extensible-host-controler-interface-usb-xhci.pdf in Intel's HP. https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf I read "4.19.1.1 state machine" and "4.19.6 Port Test Modes" in this document. I think that the sequence in "4.19.6 Port Test Modes" is not done by "case USB_PORT_FEAT_TEST statement block".

My test enviroment.
Target board : Jetson TX1 Developer Kit
code : L4T Sources 24.2.1 http://developer.nvidia.com/embedded/dlc/l4t-sources-24-2-1
lsusb dump : Insert Transcend’s USB memory in USB3.0 type A port.

Bus 002 Device 002: ID 0955:09ff NVidia Corp.
Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 001 Device 002: ID 1307:0163 Transcend Information, Inc. 256MB/512MB/1GB Flash Drive
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub

“code inserted printk statement”

diff --git a/kernel/drivers/usb/host/xhci-hub.c b/kernel/drivers/usb/host/xhci-hub.c

--- a/kernel/drivers/usb/host/xhci-hub.c
+++ b/kernel/drivers/usb/host/xhci-hub.c
@@ -20,6 +20,7 @@
  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+#include <linux/init.h>
 #include <linux/gfp.h>
 #include <asm/unaligned.h>
 #include <linux/usb/otg.h>
@@ -555,17 +556,27 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
        u16 wake_mask = 0;
        u16 timeout = 0;
        u16 test_selector = 0;
+       int i;
 
        max_ports = xhci_get_ports(hcd, &port_array);
        bus_state = &xhci->bus_state[hcd_index(hcd)];
 
+       printk("test msg : file %s : typeReq[%x] wValue[%x] wIndex[%x] wLength[%x] buf = [",__func__,typeReq,wValue,wIndex,wLength);
+       for(i=0;i < wLength ; i++)
+       {
+               printk("%x ",buf[i]);
+       }
+       printk("]\n");
+
@@ -931,11 +954,18 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
                        if (xhci_halt(xhci))
                                goto error;
 
+                       temp = xhci_readl(xhci, port_array[wIndex]);
+                       printk("test msg Before PORTSC [%x], index [%x] \n",temp,wIndex );
                        /* Start test mode in PORTPMSC */
                        temp = xhci_readl(xhci, port_array[wIndex] + 1);
                        temp = xhci_port_state_to_neutral(temp);
+                       test_selector = 0x04;
                        temp |= test_selector << 28;
                        xhci_writel(xhci, temp, port_array[wIndex] + 1);
+
+                       temp = xhci_readl(xhci, port_array[wIndex]);
+                       printk("test msg After PORTSC [%x], index [%x] \n",temp,wIndex );
+                       temp = xhci_readl(xhci, port_array[wIndex]+1);
+                       printk("test msg PORTPMSC [%x] \n",temp);
                        break;

" tegra_hc_port_test_v3_static log " I confirmed test packet waveform with oscilloscope.

test msg : file xhci_hub_control : typeReq[a300] wValue[0] wIndex[1] wLength[4] buf = [20 79 40 ad ]
test msg : file xhci_hub_control : typeReq[a300] wValue[0] wIndex[2] wLength[4] buf = [20 79 40 ad ]
test msg : file xhci_hub_control : typeReq[a300] wValue[0] wIndex[3] wLength[4] buf = [20 79 40 ad ]
test msg : file xhci_hub_control : typeReq[2301] wValue[10] wIndex[3] wLength[0] buf = []
test msg : file xhci_hub_control : typeReq[a300] wValue[0] wIndex[4] wLength[4] buf = [20 79 40 ad ]
test msg : file xhci_hub_control : typeReq[a300] wValue[0] wIndex[5] wLength[4] buf = [20 79 40 ad ]
test msg : file xhci_hub_control : typeReq[a300] wValue[0] wIndex[3] wLength[4] buf = [10 fb cb fd ]
test msg : file xhci_hub_control : typeReq[2303] wValue[4] wIndex[3] wLength[0] buf = []
test msg : file xhci_hub_control : typeReq[a300] wValue[0] wIndex[3] wLength[4] buf = [f0 f8 cb fd ]
test msg : file xhci_hub_control : typeReq[2301] wValue[14] wIndex[3] wLength[0] buf = []
test msg : file xhci_hub_control : typeReq[2301] wValue[8] wIndex[2] wLength[0] buf = []
test msg : file xhci_hub_control : typeReq[2303] wValue[15] wIndex[402] wLength[0] buf = []
test msg SetPortFeature USB_PORT_FEAT_TEST
test msg Before PORTSC [80], index [1]
test msg After PORTSC [80], index [1]
test msg PORTPMSC [0]
test msg : file xhci_hub_control : typeReq[2303] wValue[4] wIndex[3] wLength[0] buf = []
test msg : file xhci_hub_control : typeReq[a300] wValue[0] wIndex[3] wLength[4] buf = [50 f8 25 ef ]
test msg : file xhci_hub_control : typeReq[2301] wValue[14] wIndex[3] wLength[0] buf = []

“your script log”

test msg : file xhci_hub_control : typeReq[a300] wValue[0] wIndex[1] wLength[4] buf = [20 79 20 fe ]
test msg : file xhci_hub_control : typeReq[a300] wValue[0] wIndex[2] wLength[4] buf = [20 79 20 fe ]
test msg : file xhci_hub_control : typeReq[a300] wValue[0] wIndex[3] wLength[4] buf = [20 79 20 fe ]
test msg : file xhci_hub_control : typeReq[2301] wValue[10] wIndex[3] wLength[0] buf = []
test msg : file xhci_hub_control : typeReq[a300] wValue[0] wIndex[4] wLength[4] buf = [20 79 20 fe ]
test msg : file xhci_hub_control : typeReq[a300] wValue[0] wIndex[5] wLength[4] buf = [20 79 20 fe ]
test msg : file xhci_hub_control : typeReq[a300] wValue[0] wIndex[3] wLength[4] buf = [10 fb cb fd ]
test msg : file xhci_hub_control : typeReq[2303] wValue[4] wIndex[3] wLength[0] buf = []
test msg : file xhci_hub_control : typeReq[a300] wValue[0] wIndex[3] wLength[4] buf = [f0 f8 cb fd ]
test msg : file xhci_hub_control : typeReq[2301] wValue[14] wIndex[3] wLength[0] buf = []
test msg : file xhci_hub_control : typeReq[a006] wValue[2900] wIndex[0] wLength[f] buf = [d0 7c 65 ef c0 ff ff ff 64 43 65 0 c0 ff ff ]
test msg : file xhci_hub_control : typeReq[2303] wValue[15] wIndex[102] wLength[0] buf = []
test msg SetPortFeature USB_PORT_FEAT_TEST
test msg Before PORTSC [2a0], index [1]
test msg After PORTSC [2a0], index [1]
test msg PORTPMSC [f0000000]
test msg : file xhci_hub_control : typeReq[2303] wValue[4] wIndex[3] wLength[0] buf = []
test msg : file xhci_hub_control : typeReq[a300] wValue[0] wIndex[3] wLength[4] buf = [50 38 ba b0 ]
test msg : file xhci_hub_control : typeReq[2301] wValue[14] wIndex[3] wLength[0] buf = []
test msg : file xhci_hub_control : typeReq[2301] wValue[1] wIndex[3] wLength[0] buf = []

Hi yasuhiro,
Please do direct register write.

PORTPMSC is defined in standard XHCI specifications.

===
5.4.9 Port PM Status and Control Register (PORTPMSC)
Address: Operational Base + (404h + (10h * (n-1)))
where: n = Port Number (Valid values are 1, 2, 3, … MaxPorts)
===

Base address of Tegra XHCI mmio region is 0x70090000. Tegra XHCI operational base is 0x70090020 because capability registers occupies 0x20 bytes.
Address of PORTPMSC for n-th port is "0x70090020 + (404h + (10h * (n-1)))".

Hi yasuhiro, how’s it going with direct reg write?

Hi DaneLLL
Sorry for my late reply.
I wrote direct register via “/dev/mem” file.

But this way is failed.
I could not observe not only test_j but also test_packet.
Probably I think my code’s step does not conform to standard XHCI specifications.

Code is here.

#define BASE_ADDR	0x70090020
#define PORTPMSC	0x404
#define PORT_OFFSET	0x10
#define PAGE_SIZE	(1UL << 12)
#define MASK		0xF0000000
#define TEST_J		0x10000000

volatile void *map;
char *addr;
int fd = 0;	
int mod = (BASE_ADDR+PORTPMSC + PORT_OFFSET*(2-1));	//Test Port 2.
int poff = 0;
int writeData = 0
	
poff = (BASE_ADDR + PORTPMSC + PORT_OFFSET -mod)%PAGE_SIZE; 
fd = open("/dev/mem", O_RDWR | O_SYNC , 0);

map = mmap(0, PAGE_SIZE-1, PROT_READ|PROT_WRITE, MAP_SHARED, fd, (BASE_ADDR + PORTPMSC + PORT_OFFSET -mod)-poff);
addr = map + poff + mod;
memcpy(&writeData,phy_addr,8);
writeData = writeData&(~MASK) | TEST_J;
memcpy(phy_addr,&writeData,8);
munmap((void *)iomap,PAGE_SIZE-1);

Hi yasuhiro, are you able to get TEST_PACKET with the same code?

Hi.

Oh sorry. My posted code is wrong.Does not work correctly.

I repost the code that I actually tested TEST_PACKET.
*I could not observe TEST_PACKET with following code.

#include <sys/mman.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <unistd.h>
#include <stdio.h>
#include <string.h>

#define PAGE_SIZE       (1UL << 12)
#define BASE_ADDR       0x70090020
#define PORT_OFFSET     0x10
#define PORT_NUM        0x10 //Per
#define PORTPSC         0x400
        #define PORTPSC_MASK_RSVD_Z  ((1UL << 2) | (1UL << 19) | (1UL << 23) | (1UL << 28) | (1UL << 29) | (1UL << 31))
        #define PORTPSC_PP  0x00000200
#define PORTPMSC        0x404
        #define PORTPMSC_MASK   0xF0000000
        #define TEST_J          0x10000000
        #define TEST_K          0x20000000
        #define TEST_SE0NAK 0x30000000
        #define TEST_PACKET 0x40000000
        #define TEST_FORCEEN 0x50000000

struct TestCase{
        char *name;
        unsigned int reg_addr;
};

void printHex2Bin(unsigned int addr,char *data , int len);
void portPowerOff(char *addr);

int main(int argc, char *argv[])
{
        volatile void *map;
        char *addr;
        char *temp_addr;
        char *arg;
        int fd = 0;
        int poff = 0;
        char byte_array[8];
        unsigned int *portsc_data;
        unsigned int *portpmsc_data;
        unsigned int test_select = TEST_PACKET;
        int port_no = 2;

        //File Open.
        fd = open("/dev/mem", O_RDWR | O_SYNC , 0);
        poff = BASE_ADDR%PAGE_SIZE;
        map = mmap(0, PAGE_SIZE-1, PROT_READ|PROT_WRITE, MAP_SHARED, fd, BASE_ADDR-poff);
        addr = (char *)map + poff;      // BASE_ADDR.

        portsc_data = (unsigned int *)&byte_array[0];
        portpmsc_data = (unsigned int *)&byte_array[4];

        // ACCESS PORTSC and PORTPMSC
        //Target is PORTSC T_XUSB_XHCI_OP_PORTSC_PP and PORTPMSC T_XUSB_XHCI_OP_PORTPMSCHS_TM
        addr = addr + PORTPSC + PORT_OFFSET*(port_no-1);
        memcpy(byte_array,addr,8);
        *portsc_data = *portsc_data&(~(PORTPSC_MASK_RSVD_Z|PORTPSC_PP));
        *portpmsc_data = *portpmsc_data&(~PORTPMSC_MASK) | test_select;
        memcpy(addr,byte_array,8);
        usleep(2);
        memcpy(byte_array,addr,8);

        munmap((void *)map,PAGE_SIZE-1);
    close(fd);

}

Hi yasuhiro,
Not sure but the port number seems wrong. Shouldn’t it be 3?
Sine you are able to get TEST_PACKET via tegra_hc_port_test_v3_static. Please compare the register value with it.

Hi DaneLLL.

Of course I’m going to have to understand your advice.
For confirmation I modified code and run test. But I couldn’t observed TEST_PACKET.
diff line 44

  • “int port_no = 2;”
  • “int port_no = 3;”

So I compared register dump before and after running script"tegra_hc_port_test_v3_static -x 2".

  • Command “tegra_hc_port_test_v3_static -x 2” has been successfully tested TEST_PACKET.
    The difference especially appeared in 70090474 .
    It seems that the allocation of registers is different from “404h + 10h*(n-1)”.
    Now I am trial and error condition.

register dump after bootup Ubuntu.

LSB->MSB
Address 70090020         05 00 00 00 00 00 00 00
Address 70090028         01 00 00 00 00 00 00 00
Address 70090030         00 00 00 00 02 00 00 00
Address 70090038         08 00 00 00 00 00 00 00
Address 70090040         00 00 00 00 00 00 00 00
Address 70090048         00 00 00 00 00 00 00 00
Address 70090050         00 10 03 80 00 00 00 00
Address 70090058         24 00 00 00 00 00 00 00
Address 70090060         00 00 00 00 00 00 00 00
~
Address 70090400         00 00 00 00 00 00 00 00
Address 70090408         00 00 00 00 00 00 00 00
Address 70090410         00 00 00 00 00 00 00 00
Address 70090418         00 00 00 00 00 00 00 00
Address 70090420         03 12 00 00 00 00 00 00
Address 70090428         00 00 00 00 00 00 00 00
Address 70090430         a0 02 00 00 00 00 00 00
Address 70090438         00 00 00 00 00 00 00 00
Address 70090440         a0 02 00 00 00 00 00 00
Address 70090448         00 00 00 00 00 00 00 00
Address 70090450         a0 02 00 00 00 00 00 00
Address 70090458         00 00 00 00 00 00 00 00
Address 70090460         a0 02 00 00 00 00 00 00
Address 70090468         00 00 00 00 00 00 00 00
Address 70090470         a0 02 00 00 00 00 00 00
Address 70090478         00 00 00 00 00 00 00 00
Address 70090480         03 0e 00 00 00 00 00 00
Address 70090488         00 00 00 00 00 00 00 00
Address 70090490         a0 02 00 00 00 00 00 00
Address 70090498         00 00 00 00 00 00 00 00
Address 700904a0         a0 02 00 00 00 00 00 00
Address 700904a8         00 00 00 00 00 00 00 00
Address 700904b0         a0 02 00 00 00 00 00 00
Address 700904b8         00 00 00 00 00 00 00 00
Address 700904c0         a0 02 00 00 00 00 00 00
Address 700904c8         00 00 00 00 00 00 00 00
Address 700904d0         a0 02 00 00 00 00 00 00
Address 700904d8         00 00 00 00 00 00 00 00
Address 700904e0         a0 02 00 00 00 00 00 00
Address 700904e8         00 00 00 00 00 00 00 00
Address 700904f0         a0 02 00 00 00 00 00 00
Address 700904f8         00 00 00 00 00 00 00 00
Address 70090500         a0 02 00 00 00 00 00 00
Address 70090508         00 00 00 00 00 00 00 00
Address 70090510         a0 02 00 00 00 00 00 00
Address 70090518         00 00 00 00 00 00 00 00

register dump after run tegra_hc_port_test_v3_static.

LSB->MSB
Address 70090020         00 00 00 00 01 00 00 00
Address 70090028         01 00 00 00 00 00 00 00
Address 70090030         00 00 00 00 02 00 00 00
Address 70090038         00 00 00 00 00 00 00 00
Address 70090040         00 00 00 00 00 00 00 00
Address 70090048         00 00 00 00 00 00 00 00
Address 70090050         00 10 03 80 00 00 00 00
Address 70090058         24 00 00 00 00 00 00 00
Address 70090060         00 00 00 00 00 00 00 00
~
Address 70090420         03 12 00 00 00 00 00 00
Address 70090428         00 00 00 00 00 00 00 00
Address 70090430         a0 02 00 00 00 00 00 00
Address 70090438         00 00 00 00 00 00 00 00
Address 70090440         a0 02 00 00 00 00 00 00
Address 70090448         00 00 00 00 00 00 00 00
Address 70090450         a0 02 00 00 00 00 00 00
Address 70090458         00 00 00 00 00 00 00 00
Address 70090460         a0 02 00 00 00 00 00 00
Address 70090468         00 00 00 00 00 00 00 00
Address 70090470         60 03 00 00 00 00 00 40
Address 70090478         00 00 00 00 00 00 00 00
Address 70090480         03 0e 00 00 00 00 00 00
Address 70090488         00 00 00 00 00 00 00 00
Address 70090490         a0 02 00 00 00 00 00 00
Address 70090498         00 00 00 00 00 00 00 00
Address 700904a0         a0 02 00 00 00 00 00 00
Address 700904a8         00 00 00 00 00 00 00 00
Address 700904b0         a0 02 00 00 00 00 00 00
Address 700904b8         00 00 00 00 00 00 00 00
Address 700904c0         a0 02 00 00 00 00 00 00
Address 700904c8         00 00 00 00 00 00 00 00
Address 700904d0         a0 02 00 00 00 00 00 00
Address 700904d8         00 00 00 00 00 00 00 00
Address 700904e0         a0 02 00 00 00 00 00 00
Address 700904e8         00 00 00 00 00 00 00 00
Address 700904f0         a0 02 00 00 00 00 00 00
Address 700904f8         00 00 00 00 00 00 00 00
Address 70090500         a0 02 00 00 00 00 00 00
Address 70090508         00 00 00 00 00 00 00 00
Address 70090510         a0 02 00 00 00 00 00 00
Address 70090518         00 00 00 00 00 00 00 00

Hi DaneLLL.
I succeeded the test(TEST_J/TEST_K/TEST_PACKET etc).

I modified my code to conform to standard XHCI specifications.

• Disable all Device Slots.
• All ports shall be in the Disabled state (PP = ‘0’).
• Set the Run/Stop (R/S) bit in the USBCMD register to a ‘0’ and wait for the HCHalted (HCH) bit in
the USBSTS register, to transition to a ‘1’. Note that an xHC implementation shall not allow port
testing with the R/S bit set to a ‘1’.
• Set the Port Test Control field in the port under test PORTPMSC register to the value
corresponding to the desired test mode.
• For USB2 ports, if the selected test is Test_Force_Enable, then after selecting the test the
Run/Stop (R/S) bit in the USBCMD register shall then be transitioned back to ‘1’ by software,
in order to enable transmission of SOFs out of the port under test.
• When the test is complete, if the xHC is running system software shall clear the R/S bit and ensure
the host controller is halted (HCHalted (HCH) bit is a ‘1’).
• Terminate and exit test mode by setting HCRST to a ‘1’.

And I specified port number 7. Why is number 7? I don’t know well.
As a result, Jetson TX1 Developer kit device output waveform.

Hi Yasuhiro/DaneLLL,

I want to test USB Port 2.0 and 3.0 on our custom board based on Tegra K1 using (test J, test K, test SEO NAK, and test packet).

I have downloaded Two applications (“tegra_ehci_port_test” and “tegra_hc_port_test_v3_static”) and document.
In Document “Tegra K1 USB 2.0 Compliance Test Tools” Registers for Host testing are given.

As per document i need to run application to send Test Packet.
I have some queries regarding this testing,

  1. do i need to set host registers for (test J, test K, test SEO NAK, and test packet) before running the above test applications?
  2. If yes then from where can i set registers (changes in xhci-hub driver? OR create Test Application with MMAP)?
  3. If I need to create test application then what is the correct register address for USB 3.0(xUSB) port as it is not provided in document?

Thanks in Advance.