Hello,
A major party-stopper for my effort to add a different CSI camera :(
I am trying to add a ov13850 camera in the place of the default ov5693. So I took the following steps:
-
Copied the drivers/media/platform/tegra/ov5693.c to drivers/media/platform/tegra/ov13850.c to have a starting point, then renamed all methods to contain the new name
-
Copied entries to create another profile
In arch/arm64/boot/dts/tegra210-platforms/tegra210-jetson-cv-camera-e3326-a00.dtsi
camera-pcl {
compatible = "nvidia,tegra210-camera", "simple-bus";
configuration = <0xAA55AA55>;
modules {
module0: module0@modules {
compatible = "sensor,front";
badge_info = "e3326_front_P5V27C";
sensor {
profile = <&ov13850_2>;
platformdata = "t210ref_ov5693f_pdata";
};
};
};
profiles {
ov5693_2: ov5693-pcl@2_0037 {
index = <0>;
chipname = "pcl_OV5693f";
type = "sensor";
guid = "sOV5693f";
position = <0>;
bustype = "i2c";
busnum = <CAM_I2C_BUS>;
addr = <0x37>;
datalen = <2>;
pinmuxgrp = <0xFFFF>;
gpios = <2>;
regulators = "vana", "vif";
clocks = "cam_mclk1";
drivername = "ov5693.1";
devid = <0x5693>;
poweron = <
CAMERA_IND_CLK_SET(10000)
CAMERA_GPIO_CLR(CAM0_PWDN)
CAMERA_GPIO_CLR(CAM0_RST_L)
CAMERA_WAITMS(1)
CAMERA_REGULATOR_ON(0)
CAMERA_REGULATOR_ON(1)
CAMERA_WAITMS(1)
CAMERA_GPIO_SET(CAM0_PWDN)
CAMERA_GPIO_SET(CAM0_RST_L)
CAMERA_WAITMS(10)
CAMERA_END
>;
poweroff = <
CAMERA_IND_CLK_CLR
CAMERA_GPIO_CLR(CAM0_PWDN)
CAMERA_GPIO_CLR(CAM0_RST_L)
CAMERA_WAITUS(10)
CAMERA_REGULATOR_OFF(1)
CAMERA_REGULATOR_OFF(0)
CAMERA_END
>;
/* sensor capabilities */
cap-version = <0x34340002>;
cap-identifier = "OV5693.1";
cap-sensor_nvc_interface = <5>;
cap-pixel_types = <0x101>;
cap-orientation = <1>;
cap-direction = <1>;
cap-initial_clock_rate_khz = <6000>;
cap-h_sync_edge = <0>;
cap-v_sync_edge = <0>;
cap-mclk_on_vgp0 = <0>;
cap-csi_port = <1>;
cap-data_lanes = <2>;
cap-virtual_channel_id = <0>;
cap-discontinuous_clk_mode = <0>;
cap-cil_threshold_settle = <0>;
cap-min_blank_time_width = <16>;
cap-min_blank_time_height = <16>;
cap-preferred_mode_index = <0>;
cap-external_clock_khz_0 = <24000>;
cap-clock_multiplier_0 = <8000000>;
cap-external_clock_khz_1 = <0>;
cap-clock_multiplier_1 = <0>;
cap-hdr-enabled;
};
ov13850_2: ov13850-pcl@2_0020 {
index = <0>;
chipname = "pcl_OV13850f";
type = "sensor";
guid = "sOV13850f";
position = <0>;
bustype = "i2c";
busnum = <CAM_I2C_BUS>;
addr = <0x20>;
datalen = <2>;
pinmuxgrp = <0xFFFF>;
gpios = <2>;
regulators = "vana", "vif", "vdig";
clocks = "cam_mclk1";
drivername = "ov13850.1";
devid = <0xD850>;
poweron = <
CAMERA_IND_CLK_SET(10000)
CAMERA_GPIO_CLR(CAM0_PWDN)
CAMERA_GPIO_CLR(CAM0_RST_L)
CAMERA_WAITMS(1)
CAMERA_REGULATOR_ON(0)
CAMERA_REGULATOR_ON(1)
CAMERA_WAITMS(1)
CAMERA_GPIO_SET(CAM0_PWDN)
CAMERA_GPIO_SET(CAM0_RST_L)
CAMERA_WAITMS(10)
CAMERA_END
>;
poweroff = <
CAMERA_IND_CLK_CLR
CAMERA_GPIO_CLR(CAM0_PWDN)
CAMERA_GPIO_CLR(CAM0_RST_L)
CAMERA_WAITUS(10)
CAMERA_REGULATOR_OFF(1)
CAMERA_REGULATOR_OFF(0)
CAMERA_END
>;
/* sensor capabilities */
cap-version = <0x34340002>;
cap-identifier = "OV13850.1";
cap-sensor_nvc_interface = <5>;
cap-pixel_types = <0x101>;
cap-orientation = <1>;
cap-direction = <1>;
cap-initial_clock_rate_khz = <6000>;
cap-h_sync_edge = <0>;
cap-v_sync_edge = <0>;
cap-mclk_on_vgp0 = <0>;
cap-csi_port = <1>;
cap-data_lanes = <4>;
cap-virtual_channel_id = <0>;
cap-discontinuous_clk_mode = <0>;
cap-cil_threshold_settle = <0>;
cap-min_blank_time_width = <16>;
cap-min_blank_time_height = <16>;
cap-preferred_mode_index = <0>;
cap-external_clock_khz_0 = <24000>;
cap-clock_multiplier_0 = <8000000>;
cap-external_clock_khz_1 = <0>;
cap-clock_multiplier_1 = <0>;
cap-hdr-enabled;
};
};
};
and in arch/arm64/boot/dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
camera-pcl {
profiles {
ov5693-pcl@2_0037 {
use_of_node = "yes";
dev_name = "ov5693";
num = <1>;
vana-supply = <&en_vdd_cam_hv_2v8>;
vif-supply = <&en_vdd_cam>;
vdig-supply = <&en_vdd_cam_1v2>;
cam2-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
};
ov13850-pcl@2_0020 {
use_of_node = "yes";
dev_name = "ov13850";
num = <1>;
vana-supply = <&en_vdd_cam_hv_2v8>;
vif-supply = <&en_vdd_cam>;
vdig-supply = <&en_vdd_cam_1v2>;
cam2-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
};
};
};
- So now I have a folder named:
/sys/class/misc/ov13850.1/
and debug contents like this:
root@tegra-ubuntu:~# cat /sys/kernel/debug/camera.pcl/d
734f563133383530 sensor ov13850.1 0 6 20 2 0000d850 9b pcl_OV13850f
camera.pcl: camera devices supported:
pcl_OV13850f: type 0, ref_cnt 0. 16 bit addr, 08 bit data, stride 0, pad 0 bits. cache type: 0, flags r 00 / w 00
camera.pcl: No device installed.
camera.pcl: No App running.
platform data: cfg = aa55aa55
{ sensor ov13850.1 @20, } *
- Hoping this looks cool enough, I started gstreamer lone that worked ok with the default camera:
root@tegra-ubuntu:~# gst-launch-1.0 nvcamerasrc sensor-id=0 tnr-mode=NoiseReduction_HighQuality tnr-strength=1.0 intent=video ! 'video/x-raw(memory:NVMM), width=(int)2592, height=(int)1944, format=(string)I420, framerate=(fraction)30/1' ! omxh265enc ! fakesink
Invalid FPSRange Input
Setting pipeline to PAUSED ...
Inside NvxLiteH264DecoderLowLatencyInitNvxLiteH264DecoderLowLatencyInit set DPB and MjstreamingInside NvxLiteH265DecoderLowLatencyInitNvxLiteH265DecoderLowLatencyInit set DPB and MjstreamingSocket read error. Camera Daemon stopped functioning.....
gst_nvcamera_open() failed ret=0
ERROR: Pipeline doesn't want to pause.
Setting pipeline to NULL ...
Freeing pipeline ...
I am sure there is some mystery going on with the gst plugin for the camera, but really, how does it distinguishes between my camera and the stock one. I hope name is not hardcoded or something like it. And why doens’t it even try to open the camera at all?
Any help would be appreciated :)