How to Adjustment MIPI DSI signal driven strength for TX2

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

Hi,

We had MIPI DSI display issue,
Could you please tell us how to adjust MIPI DSI signal driven strength for TX2?

We use MIPI DSI signal as below,
DSI0_CLKP
DSI0_CLKN

DSI0_D0P
DSI0_D0N

DSI0_D1P
DSI0_D1N

DSI1_D0P
DSI1_D0N

DSI1_D1P
DSI1_D1N

thanks

2

Hi Kevin,

Please check the tuning guide of TX1 first, it could work for TX2 too: [url]http://developer.nvidia.com/embedded/dlc/jetson-tx1-mipi-dsi-csi-design-and-tuning-guide[/url]

3

Hi Trumany,

I’m not clearly understand the tuning steps in the guide book.

Is that means we have to do the MIPI calibration first, and after we get the register from the calibration debug report then using “devmem2” do the signal driven strength right?

If that so, may I ask how to do the MIPI calibration correctly or how to get the DSI register properly?
Appreciated for any help.

Thanks,

John

4

devmem2 is the tool for implementing the setting command, even the calibration is done with it. Please read the ‘Example of Devmem2 usage’ in guide for details, and you can find the related registers in TRM.

5

Hi Trumany,
I followed document to R/W register but still not work.
Such as DIS base address:15300000
Register “DSI_PAD_CONTROL_2_0” offset:0x51
Command: sudo devmem2 0x15300051
but it feedback error information as below:
/dev/mem opened.
Memory mapped at[ 6952.142221] Unhandled fault: alignment fault (0x92000021) at 0x0000007f891f5144 address 0x7f891f5000.
Bus error (core dumped)

Could you help me to check this error information?

6

The base address of DSI_PADCTL is 0x15880000.

7

Hi Trumany,

We try to use 0x15880051 and we got the same fault information as below:
/dev/mem opened.
Memory mapped at[ 1480.809611] Unhandled fault: alignment fault (0x92000021) at 0x0000007f91063051 address 0x7f91063000.
Bus error (core dumped)

8

hank_chiang,

Please refer to dsi driver(dsi.c) under our kernel source.

The function tegra_dsi_writel() or tegra_dsi_readl() indicates the correct register and offset value.

For the offest, below is for tx2.

GET_BYTE_OFFSET(reg)    ((reg > 8) ? ((reg + 1) * 4) : (reg * 4))