Yes it works. But this method is not suitable for me. I don’t want change default *.cfg files, because its add complexity to patching SDK. I just want to change pinmux regs in the CBoot runtime as it does when the Linux kernel boots.
I used bootloader/t186ref/BCT/tegra19x-mb1-pinmux-p3668-a01.cfg and “Xavier Series SoC Technical Reference Manual” (for check) to get addresses. Also, I found macros NV_ADDRESS_MAP_PADCTL_A0_BASE in CBoot code that evaluates as padctl regs base address (0x2430000).
For example, reg PADCTL_UART_SPI1_SCK_0 (GPIO Z3) have offset 0x40 in PADCTL_A13 (0x0243d000), then I get the full address using expression NV_ADDRESS_MAP_PADCTL_A0_BASE + 0xd040.
To access the GPIO I am using this CBoot driver as you mentioned. But unfortunately the function call gpio_config(gpio_main_drv, TEGRA_GPIO(Z, 3), GPIO_PINMODE_OUTPUT) does not change the pin direction from default input to output.
Instead, I found that pinmux configuration for MB1 in .cfg file works well. But this solution does not suit me.
let’s back to your original question,
may I know what’s the actual use-case to change the pinmux settings for those 4 GPIOs/pins in CBoot.
could you please also share diff file to indicate all the cboot changes you’ve done for reference.
please use the 32-bit register write marco in the NV_WRITE32(), you may also read it back and print it out to ensure you’ve gotten the correct register.
you’re not seeing it changes, perhaps you’re doing this before GPIO/pinmux initialization from the core DTSI files.