How to change the clock frequency of the can when using spe to control the can controller

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

I find some code about reset clk for can ,when user open can driver at tegra-can.c.

tegra_clk_reset_pulse(ttcan->rst, 1);

But I don’t know what the current clock frequency of can is after using this operation. Is there another way to adjust the clock frequency of can?
I did not find a relevant srtuct in clk-tegra.c
I want to modify the Nominal Bit Timing & Prescaler Register (NBTP) parameters, so I need to know and modify the clock frequency,Mainly CCLK_Freq and HCLK_Freq. thank you
In addition Where can I find a description of the spe clock tree

I found can2 clk source at trm 4.6.489 CLK_RST_CONTROLLER_CLK_SOURCE_CAN2_0,Which clock in 35.6 CAN Clock Domains is this clock source equivalent to?APB Clock (PCLK)？CAN Core Clock (CCLK)？CAN Host Clock (HCLK)？

3

Hello, 674493271
Can you check l4t-rt/freertos-common/code-common/tegra-can.c, function: mttcan_controller_init
ttcan_set_bitrate(ttcan, NBITRATE_PRESCALAR_500K, DBITRATE_PRESCALAR_2M);

Is that the config you want to change?
Generally, we do not suggest to update clock source. If the existing config can meet your requirement, that will be fine.

br
Chenjian

4

Hello,jachen
I want to set the can bus rate to 1m bit , I try to use #define NBITRATE_PRESCALAR_1M 0x1c09. But can does not work properly, I found many errors in the error register. When I tried to send data, the can bus appeared bus off

5

Hello, 674493271:
Let’s start from default setting.
With 500K, does the the CAN bus work well? Please confirm the default setting works well and then go to next move.
After changing to 1M, have you ever checked the waveform of CAN TX pin? What’s the actual clock?

br
ChenJian

6

Hello,jachen
I tried to use 500k. After I set my other equipment to 500k, I was also using the can analyzer to monitor the bus data. The data of my other devices can be captured by the can analyzer normally, but the spe cannot receive the correct data, nor can it send the data. I can’t tell you whether the can waveform sent by spe is correct. I don’t have an oscilloscope to view the waveform. I can get an oscilloscope to do this next Monday. The can sampling point of my other equipment is set to be greater than 85%, so I am wondering whether the difference in sampling points caused this problem.

7

I also have some questions about the value of NBITRATE_PRESCALAR_1M 0x1c09. According to the calculation method of 2.3.8 Nominal Bit Timing & Prescaler Register (NBTP) in the bosch user’s manual, the bit time should be 0x1c+0x09+3=40. So CCLK should be 40M. But I read clk_m is 38.4M. How is 0x1c09 calculated? Have I misunderstood the calculation method in the manual? Thank you

8

Hello,jachen
I can be sure that there is no problem with the hardware, because before I used linux, I can normally use can driver to send and receive data

9

Hello, 674493271:
What’s the SDK version you are using?
There are some clock adjustment since 32.4.3. That may be related for inaccurate clock setting for CAN. For 500K, it may have 0.2% error.
Still, please using osc to check the waveform, and let me know your results.
In addition, you can also check https://docs.nvidia.com/jetson/l4t/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide/clocks.html#wwpID0E06B0HA
Search ‘To use PLLAON as clock source’, and have a try.

br
chenjian

10

Hello,jechen
The version of tegra-l4t we use on linux is r28.2, but the demo of the SPE I am using is the latest 32.5 version. So is the version mismatch between linux sdk and spe demo causing this problem?

11

Hello, 674493271
would you please update the SPE firmware with same SDK version?
28.2 is too old.
Version mismatch may involve unexpected results, which is hard to check.

br
Chenjian

12

Hello,jachen

I am upgrading the sdk version to 32.5, if there is new progress, I will notify you

13

Hello,jachen
these picture are can bus waveform
NBITRATE_PRESCALAR_1M 0x1c09,this is default parameter

02-08-0x1c09
02-08-0x1c09480×589 4.44 KB

Consider the voltage rise time

no_up_time_0x1c09
no_up_time_0x1c09493×573 4.42 KB

Regardless of voltage rise time.
the default parameter is long than 1us,when Regardless of voltage rise time.
but Consider the voltage rise time,the deviation is 1%.
Have you adjusted this parameter according to the rise time when you set it?

NBITRATE_PRESCALAR_1M 0x1f04，this parameter is calculated by me according to the manual

20-80
20-80554×605 16 KB

Consider the voltage rise time

no up time
no up time571×594 13.2 KB

Regardless of voltage rise time.
This is the best effect, deviation is 1.1%.
but Consider the voltage rise time ,the deviation is 4%

14

Hello,
It may take time to check the frequency issue.
Can you help to check the cross-connection of CAN0 and CAN1 in 1M mode?
With same clock setting, CAN0 and CAN1 should be able to communicate without any problem, and we can confirm the issue comes from inaccurate clock.

br
ChenJian

15

Hello,
I forgot to explain another situation. I have some stm32 devices. When I connect tx2 to these devices, tx2 cannot receive the correct data and cannot send data. When I connect tx2 to a can analyzer, I find that I can send or receive data correctly. I know that the can analyzer has a strong tolerance for errors, so I think this problem should be caused by the error between the bit time of stm32 and the bit 20time of tx2. But before using linux kernel to drive can, it can communicate with stm32 normally. So I think the main problem is the clock

16

Hello,jachen
If I need to modify the clock source, do you have any recommendations?

17

Please check that and have a try.

br
ChenJian

18

hello,jachen
This method does not apply to t186, I can’t find anything related

clocks-init{
    compatible = "nvidia,clocks-config";
    disable {
        /* Edit clocks property to remove clock provider + clock id pair for PLLAON. */
    };
};

I can’t find the above things in any dts related to 186

19

O. My bad. That’s for Xavier, not TX2.
Can you have another check to enable CAN1/2 in Linux side and the issue is the same?

It may take time to check it in my side.

br
Chenjian

20

The can is work when use linux kernel drive can device

21

Hello,jachen
I change can clk source to pll_p_out0. I use osc check can bus waveform , the deviation of can bit time is small than 0.3%. Now can device is working. thank you