How to change TX2 Link Control and Link Status Registers‘s values?

T_PCIE2_RP_LINK_CONTROL_STATUS_COMMON_CLOCK_CONFIGURATION:
This bit when set indicates that this component and the component at the opposite end of this Link
are operating with a distributed common reference clock. A value of 0 indicates that this component
and the component at the opposite end of this Link are operating with asynchronous reference clock.
Components utilize this common clock configuration information to report the correct L0s and L1 Exit
Latencies.
0h: COMMON_CLOCK_CONFIGURATION_INIT (default)

is there anyone can help me?

Any specific reason why you want to change that?
FWIW, this bit gets set by the Linux kernel when both the upstream component and downstream component has Slot Clock Configuration bit set to ‘1’
You can check the code at https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/pcie/aspm.c?h=v5.9#n238