How to change xavier cphy edge delay value?

1.section 28.5.3 in Tx2’s datasheet have mentioned how to change edge delay according to Cphy data rate(show below),but it has been deleted in xavier datasheet. the same time,xavier use new software achievement(just send config to rce firmware and wait for results) which is different with tx2.but unfortunately,what we can config(list below) does’t include edge-delay :

struct nvcsi_brick_config {
/* Select PHY mode for both partitions /
uint32_t phy_mode;
Lane Swizzle control for Bricks.
* Valid in both C-PHY and D-PHY modes /
uint32_t lane_swizzle;
Lane polarity control. Value depends on PhyMode */
uint8_t lane_polarity[NVCSI_BRICK_NUM_LANES];
uint32_t __pad32;

struct nvcsi_cil_config {
/* Number of data lanes used (0-4) /
uint8_t num_lanes;
LP bypass mode (boolean) /
uint8_t lp_bypass_mode;
Set MIPI THS-SETTLE timing /
uint8_t t_hs_settle;
uint8_t t_clk_settle;
NVCSI CIL clock rate [kHz] /
uint32_t cil_clock_rate;
MIPI clock rate for D-Phy. Symbol rate for C-Phy [kHz] */
uint32_t mipi_clock_rate;
uint32_t __pad32;

so on the Xavier platform,how to change the value of edge delay?

i have added new regs to nvcsi prod according to tx2’s suggestions, just change
A/B_CPHY_INADJ_CTRL_0 to 0x1515 (old value is 0x0)
A/B_CPHY_CALIB_CTRL_0 to 0xBFC0BFC0(old value is 0xBFC8BFC8)
and then i start capture and use busybox devmem to dump regs,found
i found that A/B_CPHY_INADJ_CTRL_0 have beed changed to 0x1515,but A/B_CPHY_CALIB_CTRL_0 still keep the same.

For Xavier you still can configure the REG by csi5_phy_write() in the csi5_fops.c

it seems like that A/B_CPHY_CALIB_CTRL_0 is reconfigure by rtc firmware.
by the way,my core question is that how to receive lower rate (cphy)sensor’s data,any other ways can achieve it?

my sensor is sony gw1,and set mclk->12Mhz(3lane),and then dump regs:

you can found A/B_CPHY_CALIB_START_0 is incorrect(normal val is zero),it seems like that cphy scil is stucked in calibration.

Can you give more information about “lower rate (cphy)sensor’s data”

i want to capture data rate at 200 M Sym/s.

Want to confirm you have successful on TX2?

oh,no,i just want to find some ways to achieve it(xavier board),which is a target of ours project.

I would suggest to have you sensor bring up without configure this REG first.

do you mean that only configure sensor correctly without configure nvcsi/vi REGs?

Current driver not allow to tuning the CPHY time, however the default setting may working for it.
Why must using CPHY?

cphy is just one of ours targets.btw,do nvidia has plan to adjust driver to support tuning MIPI time ?if possible,do nvidia has plan to share the code of rce?

hello shqli_linux,

as you can see from the flash configuration, it’s rce-fw for camera-rtcpu-rce firmware.
we don’t have plan to release rce sources.