In the TRM, NVCSI_STREAM_0_PH_CHK_CTRL_0 register has crc and ecc enable bit.
However, accessing this register occurs kernel panic. Is this way right to check the CRC error? If then, how to manipulate this kind of registers (eg., NVCSI_STREAM_0_PH_CHK_CTRL_0)?
Also, I referenced this patch ( How to disable CSI mipi CRC check on Xavier? - Jetson & Embedded Systems / Jetson AGX Xavier - NVIDIA Developer Forums) to access and write register. But it shows kernel panic in Orin. Could you check this?