How to configure Security Registers (SCR)

I’m trying to understand how Security Registers are set in the boot loader for the Jetson Orin Nano.

I’ve found sources which refer to the security registers like this:
Filename: tegra194-mb1-bct-scr-cbb-mini-p3668.cfg
scr.major = 1;
scr.minor = 0;

scr.0.6 = 0x3c001010; # APS_AST_SCR_AST_GBL_SEC_CONTROL_0
scr.1.6 = 0x390003ff; # APS_AST_SCR_AST_HYP_SEC_CONTROL_0
scr.2.6 = 0x3c001010; # APS_AST_SCR_AST_REG_0_SEC_CONTROL_0
scr.3.6 = 0x3c001010; # APS_AST_SCR_AST_REG_1_SEC_CONTROL_0
scr.4.6 = 0x3c001010; # APS_AST_SCR_AST_REG_2_SEC_CONTROL_0
scr.5.6 = 0x3c001010; # APS_AST_SCR_AST_REG_3_SEC_CONTROL_0
scr.6.6 = 0x3c001010; # APS_AST_SCR_AST_REG_4_SEC_CONTROL_0

How are values such as 0x3c001010 to be configured? Nowhere seems to discuss them and it isn’t clear how these are set.

From what I understand, these security registers can be used to set them to secure so that the TrustZone Protection Controller (TZPC) is in control of them and only the secure world can access the peripheral / bus.

It’s referenced in the data sheet that the Platform Security Controller (PSC) acts as the TZPC however there is no other information about this, specifically how peripherals are set to secure so that only the secure world has access to them.

If the MB1 Security Configuration is not the place to set peripherals as Secure for the TrustZone Secure World via the TZPC then how are these set?

I would appreciate a real dev / engineer to reply rather than an LLM!

*** Please note that this reply is generated by LLM automatically ***

I’ll provide a comprehensive answer to your question about configuring security registers in the bootloader for the Jetson Orin Nano.

Security Registers and TrustZone Protection Controller (TZPC)

The security registers you mentioned (e.g., scr06, scr16, scr26, etc.) are part of the Platform Security Controller (PSC) and are used to configure the TrustZone Protection Controller (TZPC). The TZPC is responsible for controlling access to peripherals and memory regions, ensuring that only the secure world can access sensitive resources.

Configuring Security Registers

The values you provided (e.g., 0x3c001010) are likely hexadecimal representations of the security register settings. These values are typically set in the bootloader, specifically in the MB1 (Memory Boot 1) stage, which is responsible for initializing the security configuration.

To configure these security registers, you’ll need to modify the MB1 bootloader code. The exact steps will depend on the specific bootloader implementation and the development environment you’re using.

MB1 Security Configuration

The MB1 security configuration is indeed the place where you can set peripherals as secure for the TrustZone secure world via the TZPC. The MB1 bootloader is responsible for initializing the security configuration, including setting the security registers.

In the context of the Jetson Orin Nano, the MB1 bootloader is typically responsible for:

  1. Initializing the PSC and TZPC.
  2. Configuring the security registers to set peripherals as secure or non-secure.
  3. Enabling or disabling TrustZone features, such as secure boot and secure debug.

Configuring Peripherals as Secure

To set peripherals as secure, you’ll need to modify the MB1 bootloader code to configure the security registers accordingly. This typically involves setting the corresponding bits in the security registers to enable or disable access to specific peripherals.

For example, to set a peripheral as secure, you might need to set a specific bit in the scr06 register to 1. This would indicate that the peripheral is only accessible from the secure world.

Development Environment and Tools

To modify the MB1 bootloader code, you’ll need to use a development environment and tools that support the Jetson Orin Nano platform. This might include:

  1. NVIDIA’s L4T (Linux for Tegra) development environment.
  2. The NVIDIA Jetson SDK.
  3. A code editor or IDE (Integrated Development Environment) that supports the MB1 bootloader code.

Example Code

Unfortunately, I don’t have access to the specific code examples for the Jetson Orin Nano platform. However, I can provide a general example of how you might configure a security register in the MB1 bootloader code:

// Example code to configure security register scr06
#define SCR06_SECURE_BIT (1 << 0)

void configure_security_registers(void) {
    // Initialize the PSC and TZPC
    psc_init();
    tzpc_init();

    // Configure security register scr06
    uint32_t scr06_value = SCR06_SECURE_BIT;
    write_security_register(SCR06, scr06_value);
}

This example code initializes the PSC and TZPC, and then configures the scr06 security register to set a specific peripheral as secure.

Conclusion

Configuring security registers in the bootloader for the Jetson Orin Nano requires modifying the MB1 bootloader code to set peripherals as secure or non-secure. This involves initializing the PSC and TZPC, configuring the security registers, and enabling or disabling TrustZone features.

I hope this comprehensive answer helps you understand how to configure security registers in the bootloader for the Jetson Orin Nano. If you have further questions or need more specific guidance, feel free to ask.

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hello TheVisualiser,

may I have more details to configure security registers?
actually, you may refer to board configuration file, p3767.conf.common, there’s definition of SCR_CONFIG.
for instance, SCR_CONFIG="tegra234-mb2-bct-scr-p3767-0000.dts";
it’s the firewall settings, you’ll see cbb error as below when access to blocked registers.

[ 21.076889] CPU:0, Error:cbb-fabric, Errmon:2
[ 21.081268] Error Code : FIREWALL_ERR
[ 21.085375] Overflow : Multiple FIREWALL_ERR