Just configure the spix_[miso/mosi/sck]_xx as 0x00000444 and spix_csx_xxx as 0x00000448 to try.
1: Your suggestion is setting the SPI1 and SPI3 loopback mode?
2: Now i use the FPGA make the SPI1 Pin send singnal direct to the SPI2 pin for test, what’s the pinmux setting for this.
3: Would you give me the spidev_test.c code
- No, just any of SPI connect loopback with SPI2, due to you want to have SPI2 as slave.
- Don’t understand this. Should be FPGA connect to SPI2 why involve SPI1?
- You can get the source code from public, Sorry can public this with internal modification.
Hi ShaneCCC
now i am confused of the information you give me, so i want to make it clear and ask you some questions.
1: Whatever the SPI pin mode is master or slave, what’s the setting of SPI pinmux, is it part1 or part2? which is useful?
#part1
pinmux.0x0243d040 = 0x00000450; # spi1_sck_pz3: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d020 = 0x00000450; # spi1_miso_pz4: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d058 = 0x00000450; # spi1_miso_pz4: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d010 = 0x00000448; # spi1_cs0_pz6: rsvd1, pull-up, tristate-disable, input-enable, lpdr-disable
pinmux.0x0243d010 = 0x00000448; # spi1_cs0_pz6: rsvd1, pull-up, tristate-disable, input-enable, lpdr-disable
#part2
#Just configure the spix_[miso/mosi/sck]_xx as 0x00000444 and spix_csx_xxx as 0x00000448
Bank: 0 Reg: 0x0243d010 Val: 0x00000448 -> spi1_cs0_pz6
Bank: 0 Reg: 0x0243d020 Val: 0x00000444 -> spi1_miso_pz4
Bank: 0 Reg: 0x0243d040 Val: 0x00000444 -> spi1_sck_pz3
Bank: 0 Reg: 0x0243d050 Val: 0x00000448 -> spi1_cs1_pz7
Bank: 0 Reg: 0x0243d058 Val: 0x00000444 -> spi1_mosi_pz5
2: Is the setting like below just useful for loopback test?
#part2
#Just configure the spix_[miso/mosi/sck]_xx as 0x00000444 and spix_csx_xxx as 0x00000448
Bank: 0 Reg: 0x0243d010 Val: 0x00000448 -> spi1_cs0_pz6
Bank: 0 Reg: 0x0243d020 Val: 0x00000444 -> spi1_miso_pz4
Bank: 0 Reg: 0x0243d040 Val: 0x00000444 -> spi1_sck_pz3
Bank: 0 Reg: 0x0243d050 Val: 0x00000448 -> spi1_cs1_pz7
Bank: 0 Reg: 0x0243d058 Val: 0x00000444 -> spi1_mosi_pz5
3: I want to make a loopback test, which SPI group doesn’t need any hardware connection can be seted to test? for ex. SPI1 and SPI3, are they ?
Thank you for your patient answer.
Best wishes!
- Please apply part2
- No, it configure as SPI enable. Loopback test only verify if SPI function working or not.
- Just need two SPI to connect like below for example SPI1 and SPI3 for loopback test.
SPI1_MOSI<- ->SPI3_MOSI, SPI1_MISO<- ->SPI3_MISO, SPI1_CLK<–>SPI3_CLK, SP1_CS0 <–> SPI3_CS0 and SPI1_CS1->SPI3_CS1.
Hi ShaneCCC
i want to write a spidev_test.c to make a exe file to realize the reading function only.
Can you give me the -r function code? — ./spidev_test -r --receive only receive data; this should mode |= what ??
Sorry can’t public it due to internal IP concern.
thanks
Now i use the spidev_test you give to me.
Excute the command ,and it always wait, and after ctrl + c , it report the error.
root@dev-desktop:~/lab# ./spidev_test -D /dev/spidev1.0 -s12500000 -O -g6546 -r
...
root@dev-desktop:~/lab# ./spidev_test -D /dev/spidev1.0 -s12500000 -O -g6546 -r -zzz
using device: /dev/spidev1.0
setting spi mode for read,write
setting spi bpw
setting max speed for rd/wr
spi mode: 2
bits per word: 8 bytes per word: 1
max speed: 12500000 Hz (12500 KHz)
no. runs: 1
Using seed:0x610ce319
loop count = 0
............................................... ---------- wait here
^C transfer ioctl error: -1
/dev/spidev1.0: TEST FAILED !!!!! (status:-1)
====== Transfer stats ====
Receive:
total: 0B (0KiB 0MiB)
total: 0P
good: 0B (0KiB 0MiB)
good: 0P
ioerr: 1P
dataerr: 0P
Rate:
good: 0B/s (0KB/s)
good: 0P/s
packet drop: -1/10000
Total time: 5.712006s
And kernel report demsg
[14129.744015] spi-tegra124-slave c260000.spi: waiting for master was interrupted
[14129.744383] spi_master spi1: failed to transfer one message from queue
You can’t use spidev1.0 as master and slave.
i‘m confused that i only want to use the spidev1.0 as slave.
What should i change to make it only become a slave?
OK, please connect the MOSI <–> MISO to run below command.
./spidev_test -D /dev/spidev1.0 -s18000000 -n1 -g64 -zz
What can i do to make the spidev1.0 as slave and only do reading without writing ?
I guess run below command to wait data input from master.
./spidev_test -D /dev/spidev1.0 -s12500000 -O -g6546 -r -zzz
i try and below is dmesg
@dev-desktop:~/lab# ./spidev_test -D /dev/spidev1.0 -s12500000 -O -g6546 -r -zzz
using device: /dev/spidev1.0
setting spi mode for read,write
setting spi bpw
setting max speed for rd/wr
spi mode: 2
bits per word: 8 bytes per word: 1
max speed: 12500000 Hz (12500 KHz)
no. runs: 1
Using seed:0x610ce9b6
loop count = 0
[15816.830884] ERROR: could not get clock /spi@c260000:osc(2)
................................... -------------- wait here
^C[15822.712953] spi-tegra124-slave c260000.spi: waiting for master was interrupted
[15822.713321] spi_master spi1: failed to transfer one message from queue
transfer ioctl error: -1
/dev/spidev1.0: TEST FAILED !!!!! (status:-1)
====== Transfer stats ====
Receive:
total: 0B (0KiB 0MiB)
total: 0P
good: 0B (0KiB 0MiB)
good: 0P
ioerr: 1P
dataerr: 0P
Rate:
good: 0B/s (0KB/s)
good: 0P/s
packet drop: -1/10000
Total time: 5.884102s
i use spi1 aka SPI2
Now i find the board has HW problem, HW designed the SPI2_CS only can be used to output, can i make another gpio to be the CS_gpio?
OK, don’t know why get the OSC clocks failed. Maybe need further debug to get more to check it.
[15816.830884] ERROR: could not get clock /spi@c260000:osc(2)
Now i find the board has HW problem, HW designed the SPI2_CS only can be used to output, can i make another gpio to be the CS_gpio?
You can try use GPIO as CS. Have reference to below relative topic.