How to delay PCIe LTSSM start time ?

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX1
1

Hi guys,

We want to delay PCIe LTSSM start time after the AFI_PEX_CTRL_RST pulse finish.

When disable and enable the AFI_PEX_CTRL_RST, PEX0_RST will send the pulse to PCIe device.

We check the voltage waveform on an oscilloscope. It will immediately start LTSSM with PCIe device.

Now, we want to add delay time when PEX0_RST pulse finish.

So, how to delay PCIe LTSSM start time ?

Thanks!!!
BR.

Alleen Wang

2

Assuming you are on R28.2 code base, you can try the following patch with delay value according to your requirement

--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -2052,6 +2052,8 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port)

     tegra_pcie_port_reset(port);

+    mdelay(1000);
+
     /* On platforms where MXM is not directly connected to Tegra root port,
      * 200 ms delay (worst case) is required after reset, to ensure linkup
      * between PCIe switch and MXM
3

Hi Vidyas,

Thanks for your reply.
We have already added delay function to this, but it’s still not to delaying start LTSSM.

static void tegra_pcie_check_ports(struct tegra_pcie *pcie)
{
	struct tegra_pcie_port *port, *tmp;

	PR_FUNC_LINE;
	pcie->num_ports = 0;

#if defined(CONFIG_ARCH_TEGRA_21x_SOC)
	mbist_war(pcie, true);
#endif
	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
		dev_info(pcie->dev, "probing port %u, using %u lanes and lane map as 0x%x\n",
			 port->index, port->lanes, pcie->plat_data->lane_map);

		tegra_pcie_port_enable(port);

		usleep_range(4900,5100); //// <-- Add to this !!!

Would you have another suggestion ?

Thanks!!!
BR.

Alleen Wang

4

Does it mean usleep_range is not working here? This is very unlikely. What is the amount of delay you are looking to have?

5

Hi Vidyas,

We want to delay 5ms.

Base our check result, even I added this delay time after “tegra_pcie_port_enable”, LTSSM still start after PEX0_RST.

Thanks!!!
BR.

Alleen Wang

6

Are you referring to LTSSM of the connected end point or PCIe root port?
If you are referring to LTSSM of the end point, then, it is expected and is in line with spec also.
If you are referring to LTSSM of root port, then, it can start only after calling reset_control_deassert(pcie->pciex_rst); API