We sometimes see poor performance with our serial port connection @ baud 460800bps. This is directly connected to a slave mcu on the same board and signal integrity issues are not at play (checked out on scope). We see this messages in the kernel log, and we suspect that the Tegra clock is not set with the optimal clock settings to get the closest desired rate. We see the following kernel output occasionally to further validate our theory:
serial: configured rate out of supported range by -0.29 %
Looking into /sys/kernel/debug/clk/clk_summary, I see that the uart is derived from pll_p.
There are a couple of params such as:
Not completely sure what these params all actually mean. So can someone explain these parameters to me? Secondly, what can I do to these params or in the kernel to get a more accurate clock to hit the desired baud rate I want to use (460800)?