how to dial in serial clock to avoid serial: configured rate out of supported range by x% errors

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX1
1

We sometimes see poor performance with our serial port connection @ baud 460800bps. This is directly connected to a slave mcu on the same board and signal integrity issues are not at play (checked out on scope). We see this messages in the kernel log, and we suspect that the Tegra clock is not set with the optimal clock settings to get the closest desired rate. We see the following kernel output occasionally to further validate our theory:

serial: configured rate out of supported range by -0.29 %

Looking into /sys/kernel/debug/clk/clk_summary, I see that the uart is derived from pll_p.

There are a couple of params such as:
-clock
-enable_cnt
-prepare_cnt
-rate
-req_rate
-accuracy
-phase

Not completely sure what these params all actually mean. So can someone explain these parameters to me? Secondly, what can I do to these params or in the kernel to get a more accurate clock to hit the desired baud rate I want to use (460800)?

2

This has provided some more info: incorrect baud rate on tx2 serial console - Jetson TX2 - NVIDIA Developer Forums

3

hello ryeager12,

may i have more details.
for example. what’s your JetPack release.
could you share the steps about the failure.
also, what’s the reproduce rate.
thanks

4

This is on a TX1 based on JetPack 3.1 - Production Version running Xenial L4T R28.1, although we are not using JetPack. Kernel version is nvidia 4.4, which we build ourselves.

The serial traffic over that channel (ttyTHS2) is pretty reliable, but <1% of the time, we see serial problems. We see the kernel message above pretty much every boot, regardless of whether or not we notice serial issues.

Can you answer the question about what those clk_summary parameters are?

In addition, I see an Auto Baud Register in the TX1 TRM, however when I search through the kernel code, this register is not evident anywhere… is the auto baud feature usable on the TX1?

5

hello ryeager12,

Can you answer the question about what those clk_summary parameters are?
you could refer to the TX1 TRM, check the [CLOCK AND RESET CONTROLLER] chapter for more details.

BTW,
there’s error tolerance, could you please confirm the UART rate and the configured rate.
thanks