Hi NV_Team,
How to disable “ufshci@2450000”,in the compiled dtb file the “ufshci@2450000” status is disabled, but when I flash the dtb to Xavier, “ufshci@2450000” status is ‘okay’, what does it happen? (Flash dtb is success, and the DTB date is the same)
nvidia@xavier:~$ sudo cat /proc/device-tree/ufshci@2450000/status
okay
DTB Flash to Xavier
$dtc -I dtb -O dts tegra194-p2888-0001-p2822-0000.dtb > ex.dts
$vi ex.dts
ufshci@2450000 {
compatible = "tegra,ufs_variant";
reg = <0x0 0x2450000 0x0 0x4000>;
interrupts = <0x0 0x2c 0x4>;
iommus = <0x2 0x15>;
dma-coherent;
clocks = <0x4 0x49 0x4 0x4e 0x4 0x50 0x4 0x4a 0x4 0x4c 0x4 0x4d 0x4 0x4b 0x4 0x4f 0x4 0xa4 0x4 0xa3 0x4 0x66 0x4 0xe 0x4 0x97 0x4 0x79>;
clock-names = "mphy_core_pll_fixed", "mphy_l0_tx_symb", "mphy_tx_1mhz_ref", "mphy_l0_rx_ana", "mphy_l0_rx_symb", "mphy_l0_tx_ls_3xbit", "mphy_l0_rx_ls_bit", "mphy_l1_rx_ana", "ufshc", "ufsdev_ref", "pll_p", "clk_m", "mphy_force_ls_mode", "uphy_pll3";
resets = <0x5 0x27 0x5 0x28 0x5 0x29 0x5 0x2a 0x5 0x26 0x5 0x6c 0x5 0x6d 0x5 0x6e>;
reset-names = "mphy-l0-rx-rst", "mphy-l0-tx-rst", "mphy-l1-rx-rst", "mphy-l1-tx-rst", "mphy-clk-ctl-rst", "ufs-rst", "ufs-axi-m-rst", "ufshc-lp-rst";
nvidia,enable-x2-config;
nvidia,enable-scramble;
nvidia,mask-fast-auto-mode;
nvidia,max-hs-gear = <0x3>;
nvidia,max-pwm-gear = <0x4>;
vcc-max-microamp = <0x0>;
vccq-max-microamp = <0x0>;
vccq2-max-microamp = <0x0>;
nvidia,configure-uphy-pll3;
pinctrl-names = "ufs_dpd_enable", "ufs_dpd_disable";
pinctrl-0 = <0x27>;
pinctrl-1 = <0x28>;
status = "disabled";
vcc-supply = <0x22>;
vccq-supply = <0x29>;
vccq2-supply = <0x1f>;
nvidia,enable-hs-mode;
nvidia,cd-gpios = <0x2a 0x20 0x0>;
nvidia,cd-wakeup-capable;
linux,phandle = <0xf7>;
phandle = <0xf7>;
ufs_variant {
compatible = "tegra,ufs_variant";
};
hello Luna2020,
here’re several device tree files to be included, it might be overwritten by later *.dtsi files.
may I know what’s your actual use-case? thanks
Hi Jerry,
I have disabled all other dtsi files in Makefile “hardware/nvidia/platform/t19x/galen/kernel-dts/Makefile”.
dtb-$(CONFIG_ARCH_TEGRA_19x_SOC) += tegra194-p2888-0001-p2822-0000.dtb
#dtb-$(CONFIG_ARCH_TEGRA_19x_SOC) += tegra194-p2888-0001-p2822-0000-imx274-hdmi.dtb
#dtb-$(CONFIG_ARCH_TEGRA_19x_SOC) += tegra194-p2888-0001-p2822-0000-imx185_v1.dtb
#dtb-$(CONFIG_ARCH_TEGRA_19x_SOC) += tegra194-p2888-0001-p2822-0000-maxn.dtb
#dtb-$(CONFIG_ARCH_TEGRA_19x_SOC) += tegra194-p2888-0001-e3366-1199.dtb
#dtb-$(CONFIG_ARCH_TEGRA_19x_SOC) += tegra194-p2888-0006-p2822-0000.dtb
#dtb-$(CONFIG_ARCH_TEGRA_19x_SOC) += tegra194-p2888-0006-e3366-1199.dtb
#dtb-$(CONFIG_ARCH_TEGRA_19x_SOC) += tegra194-p2888-as-0006-p2822-0000.dtb
#dtb-$(CONFIG_ARCH_TEGRA_19x_SOC) += tegra194-p2888-as-p3668-p2822-0000.dtb
#dtbo-$(CONFIG_ARCH_TEGRA_19x_SOC) += tegra194-p2888-0001-p2822-0000-hdr40.dtbo
#dtbo-$(CONFIG_ARCH_TEGRA_19x_SOC) += tegra194-p2888-0001-p2822-0000-adafruit-sph0645lm4h.dtbo
#dtbo-$(CONFIG_ARCH_TEGRA_19x_SOC) += tegra194-p2888-0001-p2822-0000-fe-pi-audio.dtbo
#dtbo-$(CONFIG_ARCH_TEGRA_19x_SOC) += tegra194-p2888-0001-p2822-0000-respeaker-4-mic-array.dtbo
tegra194-p2888-0001-p2822-0000.dtb (277.5 KB)
hello Luna2020,
may I know what’s the actual use-case?
you may delete the device tree property definition with /delete-node/
if you’re going to remove that completely,
for example, /delete-node/ ufshci
thanks
Hi Jerry,
When we use “TEGRA194_AON_GPIO(EE, 0)” as a common GPIO, Xavier can’t bootup.
We found the GPIO is used in tegra194-p2888-0001-p2822-0000-common.dtsi section "ufshci@2450000 ", but it’s disabled status, and when we change to other GPIO and flash to Xavier the new dtb file, Xavier can’t bootup yet.
I didn’t find any ‘/delete-node/ ufshci’ in dtsi files, can you give some more advices.
Thanks.
Hi Jerry,
BTW, I flash the L4T-R32.5 version the ufshc@2450000 status is still ‘okay’ but when I dtc the dtb file to dtsi the status is disabled. You can try it on you Devkit.
ufshci@2450000 {
compatible = "tegra,ufs_variant";
reg = <0x0 0x2450000 0x0 0x4000>;
interrupts = <0x0 0x2c 0x4>;
iommus = <0x2 0x15>;
dma-coherent;
clocks = <0x4 0x49 0x4 0x4e 0x4 0x50 0x4 0x4a 0x4 0x4c 0x4 0x4d 0x4 0x4b 0x4 0x4f 0x4 0xa4 0x4 0xa3 0x4 0x66 0x4 0xe 0x4 0x97 0x4 0x79>;
clock-names = "mphy_core_pll_fixed", "mphy_l0_tx_symb", "mphy_tx_1mhz_ref", "mphy_l0_rx_ana", "mphy_l0_rx_symb", "mphy_l0_tx_ls_3xbit", "mphy_l0_rx_ls_bit", "mphy_l1_rx_ana", "ufshc", "ufsdev_ref", "pll_p", "clk_m", "mphy_force_ls_mode", "uphy_pll3";
resets = <0x5 0x27 0x5 0x28 0x5 0x29 0x5 0x2a 0x5 0x26 0x5 0x6c 0x5 0x6d 0x5 0x6e>;
reset-names = "mphy-l0-rx-rst", "mphy-l0-tx-rst", "mphy-l1-rx-rst", "mphy-l1-tx-rst", "mphy-clk-ctl-rst", "ufs-rst", "ufs-axi-m-rst", "ufshc-lp-rst";
nvidia,enable-x2-config;
nvidia,enable-scramble;
nvidia,mask-fast-auto-mode;
nvidia,max-hs-gear = <0x3>;
nvidia,max-pwm-gear = <0x4>;
vcc-max-microamp = <0x0>;
vccq-max-microamp = <0x0>;
vccq2-max-microamp = <0x0>;
nvidia,configure-uphy-pll3;
pinctrl-names = "ufs_dpd_enable", "ufs_dpd_disable";
pinctrl-0 = <0x29>;
pinctrl-1 = <0x2a>;
status = "disabled";
vcc-supply = <0x24>;
vccq-supply = <0x2b>;
vccq2-supply = <0x21>;
nvidia,enable-hs-mode;
nvidia,cd-gpios = <0x2c 0x20 0x0>;
nvidia,cd-wakeup-capable;
linux,phandle = <0xf0>;
phandle = <0xf0>;
ufs_variant {
compatible = "tegra,ufs_variant";
};
};
tegra194-p2888-0001-p2822-0000.dtb (276.5 KB)
hello Luna2020,
according to pinmux spreadsheets, GPIO31/GPIO3_PEE.00 has configured as GPIO pin by default.
could you please also refer to Topic 144550, for several ways to access GPIOs. such as, kernel APIs, python scripts, C++ samples.
thanks
Hi Jerry,
Yes, you are right, GPIO31/GPIO3_PEE.00 is GPIO, but we can’t configure it in gpio@c2f0000, because of ufshci@2450000 use it.
gpio@c2f0000 {
/* gpio-name for 40-pin header, gpio-name given as COL(10) x ROW(20) */
gpio-line-names = "CAN1_DOUT", "CAN1_DIN", "CAN0_DOUT", "CAN0_DIN", "", "", "", "", "GPIO8", "GPIO9",
"", "", "", "", "", "", "", "", "", "",
"", "", "", "I2C2_CLK", "I2C2_DAT", "", "", "", "", "";
gpio-one-enable { /* 12PIN_PIN31 3.3V output, but Xavier can't bootup */
gpio-hog;
output-low;
gpios = <TEGRA194_AON_GPIO(EE, 0) 0>;
label = "gpio-one-reg";
status = "okay";
};
};
hello Luna2020,
it’s device tree commands to delete nodes or property, you may refer to device tree sources for reference,
for example,
it will delete a node definition, ufshci@2450000 {...}
.
if you adding this line /delete-node/ ufshci;
into your device tree sources,
thanks
Hi Jerry,
I found the root cause of ufshci@2450000 in dtsi ‘disabled’ but after flash in Xavier is still ‘okay’, because of the plugin “fragment-tegra-ufs-lane10”.
fragment-tegra-ufs-lane10 {
odm-data = "enable-ufs-uphy-l10";
override@0 {
target = <&tegra_ufs>;
_overlay_ {
status = "okay"; //need to set disabled
};
};
};