How to enable 8-lane MIPI data (Gang mode) on Jetson Xavier nx

We don’t have option of sending two separate contents to two CSI bricks.
We have Half Line Mode
first half of the line =>Phy0{0,1,2,3…} => MIPI 1
second half of the line => Phy1{0,1,2,3…} => MIPI 2
After configuring this below is the dmesg log

nx@ubuntu:~$ sudo dmesg
[ 170.082752] tegra194-vi5 __tegra_channel_set_format: calling update_gang_mode()
[ 170.082971] tegra194-vi5 update_gang_mode: Enter
[ 170.083089] tegra194-vi5 update_gang_mode: gang_mode = 1 total_port = 2
[ 170.083226] tegra194-vi5 update_gang_mode_params: Enter
[ 170.106625] ar2020 2-0036: ar2020_power_on: power on
[ 170.106657] ar2020 2-0036: ar2020_power_on: release reset
[ 170.171526] [RCE] vi5_hwinit: firmware CL2018101701 protocol version 2.2
[ 170.260169] ar2020 2-0036: start streaming
[ 170.281029] tegra194-vi5 corr_err: discarding frame 1, flags: 0, err_data 256
[ 170.283481] [RCE] ERROR: capture-scheduler.c:2566 [capture_scheduler_thread] “Error processing event 0x100002”
[ 170.283492] [RCE] ERROR: capture-scheduler.c:2566 [capture_scheduler_thread] “Error processing event 0x100002”
[ 170.307130] tegra194-vi5 corr_err: discarding frame 2, flags: 0, err_data 256
[ 170.333172] tegra194-vi5 corr_err: discarding frame 3, flags: 0, err_data 256
[ 170.339485] [RCE] ERROR: capture-scheduler.c:2566 [capture_scheduler_thread] “Error processing event 0x100002”
[ 170.339493] [RCE] ERROR: capture-scheduler.c:2566 [capture_scheduler_thread] “Error processing event 0x100002”
[ 170.359230] tegra194-vi5 corr_err: discarding frame 4, flags: 0, err_data 256
[ 211.984245] ar2020 2-0036: stop streaming
[ 211.990295] ar2020 2-0036: ar2020_power_off: power off
[ 211.990324] ar2020 2-0036: ar2020_power_off: assert reset


hello ashwath.narasimhamurthy,

it’s discarding frame logs, it’s sometime a warning messages, due to unsuccess capture state, it’s dropping frames and issue a requeue for new buffers. so, you see those frame index has keep increasing.
flags:0 shows channel encountered uncorrectable error and must be reset.

moreover, the failure from RCE side looks it cannot receive end-of-frame.
what’s “Half Line Mode” looks like, did you update resolution settings for your v4l commands accordingly?

Resolution remains same width=5120,height=3840. Data is split across Phy0 and Phy1

Hi JerryChang,

I can get data over 8 lanes with speed 800 Mbps/lane. If I configure speed higger than 800 Mbps(1200 Mbps per lane) I didnt get data and getting errors as mentione in above posts.

Could you please let me know the gang mode maxmum bandwidth with 8 lane? I am assuming as per spec I can get 2.5 Gbps x 8 = 20Gbps, is it possible?

yes, it should be 2.5 Gbps x 8 = 20Gbps according to the spec.
may I also know which Jetpack release version you’re working with?

we are using JetPack_5.0.2_Linux and R35.1.0 release.

there’re some camera bug fixes, please try moving to the latest release, i.e. Jetpacl-5.1.2/l4t-r35.4.1 for confirmation.
as I mentioned several times. gang mode has only tested on TX2 series.

Hi JerryChang,

When I set below configuration (Figure-1), I am getting below Image(figure-2):


Here I can see the data of Sensor PHY0 (D0…D3 D8…D11 & so on) is in left side and PHY1(D4…D7 D12…D15 & so on) in right side.

With GANG mode CAMERA_GANG_L_R is right configuration which is getting selected by default image size > 1920 x 1080 when bus-width=8 in DTSI. I have configured my sensor as mentioned in Figure-3:


But I am not getting data properly with this configuration. Only few row of data is get captured.

Could you please help me to get data properly at Xavier NX end with Figure-3 Configuration.

may I know the details of front/back half of rows? did you meant the camera frames are separated by top-bottom?

No camera frame is seperated and as mentioned in Figure-3:
Row is divide into 2 halfs; front and back (left to right)
front : D0 D1 D2 D3 … D2559 — > PHY0 of Nvidia Xavier NX
back : D2560 D2561 D2562 D2563 … D5119 — > PHY1 of Nvidia Xavier NX

hello sujit.kumar,

there should be a larger delay for each PHY without data.
you may have a try to increase the timeout values for testing.
for example, #define CAPTURE_TIMEOUT_MS 2500

Hi JerryChang

Could you know how to congigure CAMERA_GANG_R_L, I can see in channel.c its hardcoded to CAMERA_GANG_L_R.
For both CAMERA_GANG_L_R and CAMERA_GANG_L_R I see same implementation.

you may update device tree for sending gang mode configurations.

Can you let me know which field of dtsi I need to configure

I am getting below image

But Left data is stored in Right and right data get stored in left

hello sujit.kumar,

I see… please give it a try to revise the kernel sources for confirmation,
for example,

static void update_gang_mode(struct tegra_channel *chan)
        if ((width > 1920) && (height > 1080)) {
                chan->gang_mode = CAMERA_GANG_L_R;   <== change this as.. right/left

No luck with sugested change.
I dont see either CAMERA_GANG_R_L or CAMERA_GANG_L_R any difference in channel.c
Is any whereelse this getting reflected?

Can we configure PHY1 read before PHY0 in driver any where ?

could you please check the offset. is it due to incorrect offset values?
or… you may dig into the configuration from the sensor side.

Hi JerryChang

Thank for reminding offset. I have shifted gang R_L offset and here we have image

Appreciate your help.

Please dont close this issue, I have couple of more issue with Gang mode like running with high frequency. I will try this week all and then you can close it.

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