How to enable F4/E4 as SPI interface to pass the loopback test on our carrier board

Hi:

I can pass the Loopback Test on TX2 dev board by short J21 pin19/21 according to the following website.
But our carrier board use SPI0_MOSI/SPI0_MISO(F4/E4) as SPI interface, after add SPIDev in kernel and modify dtb files, I can’t pass the loopback test on our carrier board. I tried to modify dtb file to enable /dev/spi0.0, /dev/spi1.0, /dev/spi2.0, /dev/spi3.0, but it doesn’t work.

https://elinux.org/Jetson/TX1_SPI
https://elinux.org/Jetson/TX2_SPI

Besides, why TX2 dev board J21 pin19/21 is SPI3 interface? The two pins connect to SPI1 as pin name, even if in Jetson-TX2-Generic-Customer-Pinmux-Template.xlsm, the customer usage is SPI4.

Attached is our schematic about SPI part.

Hi, please remove the level shift and try loopback test, seems your level shift might cause this kind of issue. SPI1 on carrier board is routed to SPI4 port of chip, please take pinmux sheet as standard.

Hi Trumany:

When I test TX2 dev board J21 pin19/21 which connect SPI1(F13/F14), I need to enable /dev/spidev3.0 can pass loopback test. while SPI0(F4/F3) if I enable /dev/spidev1.0 can pass loopback test.

So, SPI4 should enable /dev/spidev3.0 and SPI2 should enable /dev/spidev1.0?

Anyway, I can pass the loopback test, thanks!

You can figure it out from the pinmux tabel.
From picture shows the SPI2_xx is mape to SPI1. That means it’s spidev0 because software define start from 0 but HW define from 1. The table is the HW define.