how to enable max encoder clocks via tegra_multimedia_api

Robotics & Edge Computing Jetson & Embedded Systems Jetson Nano
1

In the documentation (nv4l2_nv_extensions.h) we can see

typedef struct v4l2_enc_hw_preset_type_param_
 1379 {
 1381     enum v4l2_enc_hw_preset_type hw_preset_type;
 1383     __u8 set_max_enc_clock;
 1384 }v4l2_enc_hw_preset_type_param
;

But in NvVideoEncoder.cpp there is only an implementation to add the hw_preset_type, not the “set_max_enc_clock” parameter.

int
NvVideoEncoder::setHWPresetType(v4l2_enc_hw_preset_type type)
{
    struct v4l2_ext_control control;
    struct v4l2_ext_controls ctrls;

    RETURN_ERROR_IF_FORMATS_NOT_SET();
    RETURN_ERROR_IF_BUFFERS_REQUESTED();

    memset(&control, 0, sizeof(control));
    memset(&ctrls, 0, sizeof(ctrls));

    ctrls.count = 1;
    ctrls.controls = &control;
    ctrls.ctrl_class = V4L2_CTRL_CLASS_MPEG;

    control.id = V4L2_CID_MPEG_VIDEOENC_HW_PRESET_TYPE_PARAM;
    control.value = type;

    CHECK_V4L2_RETURN(setExtControls(ctrls),
            "Setting encoder HW Preset type to " << type);
}

Is there any way of forcing that via tegra_multimedia_api?

Thanks

2

The clocks are configured with the nvpmodel tool. This tool ends up writing values to sysfs paths (you can see which paths/values in /etc/nvpmodel.conf)

If your process has root privileges, it can write the values you need to those sysfs endpoints, to configure the clocks the way you need them.

Another option might be to call setExtControls() yourself with the argument you want, instead of calling setHWPresetType(). Have you tried that?

3

Thanks for your answer. I thought that nvpmodel doesn’t control the encoders. At least the info is not shown. Is there any example about how to do it?

NVPM VERB: Config file: /etc/nvpmodel.conf
NVPM VERB: parsing done for /etc/nvpmodel.conf
NVPM VERB: Current mode: NV Power Mode: MAXN
0
NVPM VERB: PARAM CPU_ONLINE: ARG CORE_0: PATH /sys/devices/system/cpu/cpu0/online: REAL_VAL: 1 CONF_VAL: 1
NVPM VERB: PARAM CPU_ONLINE: ARG CORE_1: PATH /sys/devices/system/cpu/cpu1/online: REAL_VAL: 1 CONF_VAL: 1
NVPM VERB: PARAM CPU_ONLINE: ARG CORE_2: PATH /sys/devices/system/cpu/cpu2/online: REAL_VAL: 1 CONF_VAL: 1
NVPM VERB: PARAM CPU_ONLINE: ARG CORE_3: PATH /sys/devices/system/cpu/cpu3/online: REAL_VAL: 1 CONF_VAL: 1
NVPM VERB: PARAM CPU_A57: ARG MIN_FREQ: PATH /sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq: REAL_VAL: 1428000 CONF_VAL: 0
NVPM VERB: PARAM CPU_A57: ARG MAX_FREQ: PATH /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq: REAL_VAL: 1428000 CONF_VAL: 2147483647
NVPM VERB: PARAM GPU_POWER_CONTROL_ENABLE: ARG GPU_PWR_CNTL_EN: PATH /sys/devices/gpu.0/power/control: REAL_VAL: auto CONF_VAL: on
NVPM VERB: PARAM GPU: ARG MIN_FREQ: PATH /sys/devices/gpu.0/devfreq/57000000.gpu/min_freq: REAL_VAL: 921600000 CONF_VAL: 0
NVPM VERB: PARAM GPU: ARG MAX_FREQ: PATH /sys/devices/gpu.0/devfreq/57000000.gpu/max_freq: REAL_VAL: 921600000 CONF_VAL: 2147483647
NVPM VERB: PARAM GPU_POWER_CONTROL_DISABLE: ARG GPU_PWR_CNTL_DIS: PATH /sys/devices/gpu.0/power/control: REAL_VAL: auto CONF_VAL: auto
NVPM VERB: PARAM EMC: ARG MAX_FREQ: PATH /sys/kernel/nvpmodel_emc_cap/emc_iso_cap: REAL_VAL: 0 CONF_VAL: 0

About using the extControls there is some info here:
https://docs.nvidia.com/jetson/l4t-multimedia/group__V4L2Enc.html

We can see:

#define 	V4L2_CID_MPEG_VIDEO_MAX_PERFORMANCE   (V4L2_CID_MPEG_BASE+554)

I did a quick test adding:

struct v4l2_ext_control control;
    struct v4l2_ext_controls ctrls;
    
    memset(&control, 0, sizeof(control));
    memset(&ctrls, 0, sizeof(ctrls));

    ctrls.count = 1;
    ctrls.controls = &control;
    ctrls.ctrl_class = V4L2_CTRL_CLASS_MPEG;

    control.id = V4L2_CID_MPEG_BASE+554;;//  (V4L2_CID_MPEG_BASE+554);
    control.value = (uint8_t)1;

	ret = ctx.enc->setExtControls(ctrls);
	if (ret < 0) cout << "Setting encoder to max performance mode : fail" << endl;
	else if (ret == 0) cout << "Setting encoder to max performance mode : OK" << endl;

And it does’t throw any error, but I still see glitches and missing frames in the video once every few seconds.

Is there any way to see the freq of the encoders to check that the code actually did something?

Thanks;

4

Hi,
Please run ‘sudo tegrastats’ to check if clock of NVENC(or named MSENC in some releases) keeps at maximum and is not varying.

5

DaneLLL,

The output of “sudo tegrastats” with my application running at full power is:

RAM 1319/3963MB (lfb 571x4MB) IRAM 0/252kB(lfb 252kB) CPU [72%@1428,13%@1428,16%@1428,18%@1428] EMC_FREQ 24%@1600 GR3D_FREQ 53%@921 NVENC 716 APE 25 PLL@40.5C CPU@44C PMIC@100C GPU@41.5C AO@48C thermal@43C POM_5V_IN 6809/3972 POM_5V_GPU 2790/913 POM_5V_CPU 903/834

It’s always the same, not changing. So the command must be working fine.
Thanks.