How to enable PCIe C4 c

Jetson Thor Adaptation and Bring-Up — NVIDIA Jetson Linux Developer Guide

Following the Jetpack 7.0 developer guide, we conducted tests on the custom carrier board to verify the PCIE functionality.

After making the following modifications, the system can run normally in Flash mode, but the PCIE C4 controller cannot be used.

After making the following modifications, the system cannot be flashed properly.

During the flash process, I noticed that the serial port debugging log is as shown in the following screenshot:

Could you please give me some good suggestions?

Did you remember to change ODMDATA?

Is it referring to this kind of modification? In the development documentation, I couldn’t find how ODMDATA should be modified.

Also in the document

But with only this information, I’m not sure how to proceed with the modification.

Including removing the comments for ODMDATA in the conf file and then performing the flash operation, the log still outputs the same error.

Also, modifying the dtb file referenced by DTB_FILE will also cause the flash operation to fail. However, the information output by the serial console is different.

The following is the error message for the file output after modifying the reference of DTB_FILE. The corresponding dtb file can take effect if it is invoked by modifying the file /boot/extlinux/extlinux.conf.

NOTICE:  BL31: lts-v2.8.16(release):7a2e991
NOTICE:  BL31: Built : 17:19:22, Aug 21 2025
INFO: Initializing Hafnium (SPMC)
INFO: text: 0x2039e10000 - 0x2039e39000
INFO: rodata: 0x2039e39000 - 0x2039e43000
INFO: data: 0x2039e43000 - 0x203a4b1000
INFO: stacks: 0x203a4c0000 - 0x203a4f8000
INFO: Supported bits in physical address: 48
INFO: Stage 2 has 4 page table levels with 1 pages at the root.
INFO: Stage 1 has 4 page table levels with 1 pages at the root.
INFO: Memory range:  0x80000000 - 0x800000ff
S Memory ranges:
  [80000000 - 80000100 (1 pages)]
NS Memory ranges:
WARNING: Missing NS memory ranges, default to 1TB.
INFO: Loading VM id 0x8001: optee.
INFO: Loaded with 28 vCPUs, entry at 0x203bc20000.
INFO: Loading VM id 0x8002: standalonemm.
WARNING: Memory region security state ignored for S-EL1 partitions.
WARNING: Memory region security state ignored for S-EL1 partitions.
WARNING: Memory region security state ignored for S-EL1 partitions.
INFO: Loaded with 1 vCPUs, entry at 0x203dc20000.
INFO: Hafnium initialisation completed
VM 8001: I/TC:
VM 8001: I/TC: No non-secure external DT
VM 8001: I/TC: manifest DT found
VM 8001: I/TC: Switching console to device: /ffa-console
VM 8001: I/TC: OP-TEE version: 4.4 (gcc version 13.2.0 (crosstool-NG 1.26.0)) #2 Fri Aug 22 00:24:28 UTC 2025 aarch64
VM 8001: I/TC: WARNING: This OP-TEE configuration might be insecure!
VM 8001: I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
VM 8001: I/TC: Primary CPU initializing
VM 8001: I/TC: Test TZ root key is being used. This is insecure for shipping products!
VM 8001: I/TC: Primary CPU switching to normal world boot
NOTICE: Initialized VM: 0x8001, boot_order: 0
VM 8002:   (version 38.2.0-gcid-41844464 2025-08-22T00:23:12+00:00)
VM 8002:  Boot Complete
NOTICE: Initialized VM: 0x8002, boot_order: 1
NOTICE: Finished initializing all VMs.
NOTICE:  BL31 Boot Complete
▒▒t26x_general UEFI firmware (version 38.2.0-gcid-41844464 built on 2025-08-22T00:22:54+00:00)
▒▒swdtimer_timer_cb: failed to restart expired WDT after poll interval 57 (last 16120 start 16177 done 16177)
▒▒

























































▒▒

























































▒▒INFO: END TASK:PCIE
INFO: enter idle task.
INFO: END TASK:MB▒▒
INFO: enter idle task.
INFO: END TASK:MB▒▒
▒▒ph =▒▒ter idle ta▒▒GPC ▒▒sk.
        ▒▒> logic map: 0=>0 1=>2 2=>1
▒▒Unhandled Exception in EL3.
x30            = 0x000000000ff4103c
x0             = 0x0000000000000000
x1             = 0x00000000be000011
x2             = 0x0000000000000011
x3             = 0x0000000000000000
x4             = 0x8f145c61617a399f
x5             = 0x0000000000000001
x6             = 0x0000000000016648
x7             = 0x0000000000016680
x8             = 0x0000000001000000
x9             = 0x0000001403813000
x10            = 0x0000000400800000
x11            = 0x0000001f76bd4d54
x12            = 0x0000000000016644
x13            = 0x00000000ffffffff
x14            = 0x0000001f7ebaa000
x15            = 0x0000001f7ebaa000
x16            = 0x0000001f799a0358
x17            = 0x0000000000000000
x18            = 0x0000001f799ab250
x19            = 0x000000000ff753f0
x20            = 0x0000000000000000
x21            = 0x0000000000000000
x22            = 0x0000000000000000
x23            = 0x0000000000000000
x24            = 0x0000000000000000
x25            = 0x0000000000000000
x26            = 0x0000000000000000
x27            = 0x0000000000000000
x28            = 0x0000000000000000
x29            = 0x0000000000000000
scr_el3        = 0x000000401c07073d
sctlr_el3      = 0x0000000030cd183f
cptr_el3       = 0x0000000000000100
tcr_el3        = 0x0000000080853510
daif           = 0x00000000000002c0
mair_el3       = 0x00000000004404ff
spsr_el3       = 0x0000000040000309
elr_el3        = 0x0000001f78c96cd0
ttbr0_el3      = 0x000000000ff95001
esr_el3        = 0x00000000be000011
far_el3        = 0xcf73bf7773edf9ed
spsr_el1       = 0x0000000000000000
elr_el1        = 0x0000000000000000
spsr_abt       = 0x0000000000000000
spsr_und       = 0x0000000000000000
spsr_irq       = 0x0000000000000000
spsr_fiq       = 0x0000000000000000
sctlr_el1      = 0x0000000030d00980
actlr_el1      = 0x0000000000000000
cpacr_el1      = 0x0000000000300000
csselr_el1     = 0x0000000000000002
sp_el1         = 0x0000000000000000
esr_el1        = 0x0000000000000000
ttbr0_el1      = 0x0000000000000000
ttbr1_el1      = 0x0000000000000000
mair_el1       = 0x0000000000000000
amair_el1      = 0x0000000000000000
tcr_el1        = 0x0000000000000000
tpidr_el1      = 0x0000000000000000
tpidr_el0      = 0x0000000080000000
tpidrro_el0    = 0x0000000000000000
par_el1        = 0x0000000000000800
mpidr_el1      = 0x0000000081000000
afsr0_el1      = 0x0000000000000000
afsr1_el1      = 0x0000000000000000
contextidr_el1 = 0x0000000000000000
vbar_el1       = 0x0000000000000000
cntp_ctl_el0   = 0x0000000000000005
cntp_cval_el0  = 0x0000000275b89fb0
cntv_ctl_el0   = 0x0000000000000000
cntv_cval_el0  = 0x0000000000000000
cntkctl_el1    = 0x0000000000000000
sp_el0         = 0x0000001f799ab250
isr_el1        = 0x0000000000000040
cpuectlr_el1   = 0xc0007403c0543001
gicd_ispendr regs (Offsets 0x200 - 0x278)
 Offset:                        value
0000000000000200:               0x0000000000000000
0000000000000204:               0x0000000000000000
0000000000000208:               0x0000000000000000
000000000000020c:               0x0000000000000008
0000000000000210:               0x0000000010000000
0000000000000214:               0x0000000000000000
0000000000000218:               0x0000000000000000
000000000000021c:               0x0000000000000000
0000000000000220:               0x0000000000000000
0000000000000224:               0x0000000000000000
0000000000000228:               0x0000000000000000
000000000000022c:               0x0000000000000000
0000000000000230:               0x0000000000000000
0000000000000234:               0x0000000000000000
0000000000000238:               0x0000000080000000
000000000000023c:               0x0000000000000000
0000000000000240:               0x0000000000000000
0000000000000244:               0x0000000000000000
0000000000000248:               0x0000000000000000
000000000000024c:               0x0000000000000000
0000000000000250:               0x0000000000001800
0000000000000254:               0x0000000000000000
0000000000000258:               0x0000000000000000
000000000000025c:               0x0000000000800000
0000000000000260:               0x0000000000000000
0000000000000264:               0x0000000000000000
0000000000000268:               0x0000000000000000
000000000000026c:               0x0000000010000000
0000000000000270:               0x0000000000000000
0000000000000274:               0x0000000000000000
0000000000000278:               0x0000000000000000
000000000000027c:               0x0000000000000000

不知道用中文說會不會你比較容易理解.

你前面這裡的截圖, uphy1-config設定成0沒錯. 但我不知道為什麼你要把uphy0-config改成一個錯的值…
這兩個設定就是表格上面的數字.

好的,我刚刚测试完,只对uphy1-config修改,之后再进行flash,同样无法正常flash

操作步骤如下:

dtc -I dts -O dtb -o tegra264-bpmp-3834-0008-4071-xxxx.dtb tegra264-bpmp-3834-0008-4071-xxxx.dts
sudo cp  tegra264-bpmp-3834-0008-4071-xxxx.dtb bootloader/
sudo cp  tegra264-bpmp-3834-0008-4071-xxxx.dtb bootloader/generic/
sudo ./l4t_initrd_flash.sh y-c8-agx-thor-382 internal

y-c8-agx-thor-382.conf文件内容如下:

source "${LDK_DIR}/t264.conf.common";

DTB_FILE="tegra264-p4071-0000+p3834-0008-nv.dtb";
#DTB_FILE="y-c8-agx-thor-382.dtb";
TBCDTB_FILE="${DTB_FILE}";
BPFDTB_FILE="tegra264-bpmp-3834-0008-4071-xxxx.dtb";
#BPFDTB_FILE="tegra264-bpmp-3834-0008-4071-xxxx-c8.dtb";
BPFFILE="bootloader/bpmp_t264-TA1090SA-A1_prod.bin";

EXTERNAL_PT_LAYOUT="tools/kernel_flash/flash_l4t_t264_nvme.xml";
EMC_BCT="tegra264-p3834-0008-sdram-bct-l4t.dts";
WB0SDRAM_BCT="tegra264-p3834-0008-sdram-bct-warmboot-l4t.dts";
BPMP_MEM_CONFIG="tegra264-p3834-0008-sdram-dfs.dts";
MISC_CONFIG="tegra264-mb1-bct-misc-p3834-xxxx-p4071-0000.dts";
SCR_CONFIG="tegra264-mb2-bct-firewall-p3834-xxxx-p4071-0000.dts";
#PINMUX_CONFIG="tegra264-mb1-bct-pinmux-p3834-xxxx-p4071-0000.dts";
PINMUX_CONFIG="tegra264-mb1-bct-pinmux-p3834-xxxx-p4071-0000-c8.dts";
PMIC_CONFIG="tegra264-mb1-bct-pmic-p3834-0008-p4071-0000.dts";
PMC_CONFIG="tegra264-mb1-bct-padvoltage-p3834-xxxx-p4071-0000.dts";
DEVICEPROD_CONFIG="tegra264-mb1-bct-cprod-p3834-xxxx-p4071-0000.dts";
PROD_CONFIG="tegra264-mb1-bct-prod-p3834-xxxx-p4071-0000.dts";
#MB2_BCT="tegra264-mb2-bct-misc-p3834-xxxx-p4071-0000.dts";
MB2_BCT="tegra264-mb2-bct-misc-p3834-xxxx-p4071-0000-c8.dts";
# Rollback protection
MINRATCHET_CONFIG="tegra264-mb1-bct-ratchet-p3834-xxxx-p4071-0000.dts";
GPIOINT_CONFIG="tegra264-mb1-bct-gpioint-p3834-xxxx-p4071-0000.dts";
#UPHY_CONFIG="tegra264-mb1-bct-uphy-lanes-p4071-0000.dts";
UPHY_CONFIG="";
RAMCODE=12;

EXTERNAL_DEVICE="nvme0n1p1";
OVERLAY_DTB_FILE="L4TConfiguration.dtbo,tegra264-p4071-0000+p3834-xxxx-dynamic.dtbo";
# Uncomment below line to enable C4 RP controller in SRIS mode
ODMDATA="pcie@4_clk-scheme=1"
# Uncomment below line to enable C4 controller in Endpoint SRIS mode.
#ODMDATA="pcie-c4-endpoint-enable,pcie-c4-endpoint-use-int-refclk,pcie@4_clk-scheme=1_pcie-mode=2"

flash的时候,调试串口输出的信息如下:

▒▒INFO: END TASK:PCIE
INFO: enter idle task.
INFO: END TASK:MB▒▒
INFO: enter idle task.
INFO: END TASK:MB▒▒
▒▒ph =▒▒ter idle ta▒▒GPC ▒▒sk.
        ▒▒> logic map: 0=>0 1=>2 2=>1
▒▒Unhandled Exception in EL3.
x30            = 0x000000000ff4103c
x0             = 0x0000000000000000
x1             = 0x00000000be000011
x2             = 0x0000000000000011
x3             = 0x0000000000000000
x4             = 0x8f145c61617a399f
x5             = 0x0000000000000001
x6             = 0x0000000000016de0
x7             = 0x0000000000016e18
x8             = 0x0000000001000000
x9             = 0x0000001403813000
x10            = 0x0000000400800000
x11            = 0x0000001f76bb9d54
x12            = 0x0000000000016ddc
x13            = 0x00000000ffffffff
x14            = 0x0000001f7ebaa000
x15            = 0x0000001f7ebaa000
x16            = 0x0000001f799a0358
x17            = 0x0000000000000000
x18            = 0x0000001f799ab250
x19            = 0x000000000ff753f0
x20            = 0x0000000000000000
x21            = 0x0000000000000000
x22            = 0x0000000000000000
x23            = 0x0000000000000000
x24            = 0x0000000000000000
x25            = 0x0000000000000000
x26            = 0x0000000000000000
x27            = 0x0000000000000000
x28            = 0x0000000000000000
x29            = 0x0000000000000000
scr_el3        = 0x000000401c07073d
sctlr_el3      = 0x0000000030cd183f
cptr_el3       = 0x0000000000000100
tcr_el3        = 0x0000000080853510
daif           = 0x00000000000002c0
mair_el3       = 0x00000000004404ff
spsr_el3       = 0x0000000040000309
elr_el3        = 0x0000001f78c96cd0
ttbr0_el3      = 0x000000000ff95001
esr_el3        = 0x00000000be000011
far_el3        = 0x4ff3bf777bedfbed
spsr_el1       = 0x0000000000000000
elr_el1        = 0x0000000000000000
spsr_abt       = 0x0000000000000000
spsr_und       = 0x0000000000000000
spsr_irq       = 0x0000000000000000
spsr_fiq       = 0x0000000000000000
sctlr_el1      = 0x0000000030d00980
actlr_el1      = 0x0000000000000000
cpacr_el1      = 0x0000000000300000
csselr_el1     = 0x0000000000000002
sp_el1         = 0x0000000000000000
esr_el1        = 0x0000000000000000
ttbr0_el1      = 0x0000000000000000
ttbr1_el1      = 0x0000000000000000
mair_el1       = 0x0000000000000000
amair_el1      = 0x0000000000000000
tcr_el1        = 0x0000000000000000
tpidr_el1      = 0x0000000000000000
tpidr_el0      = 0x0000000080000000
tpidrro_el0    = 0x0000000000000000
par_el1        = 0x0000000000000800
mpidr_el1      = 0x0000000081000000
afsr0_el1      = 0x0000000000000000
afsr1_el1      = 0x0000000000000000
contextidr_el1 = 0x0000000000000000
vbar_el1       = 0x0000000000000000
cntp_ctl_el0   = 0x0000000000000005
cntp_cval_el0  = 0x000000029f0d7005
cntv_ctl_el0   = 0x0000000000000000
cntv_cval_el0  = 0x0000000000000000
cntkctl_el1    = 0x0000000000000000
sp_el0         = 0x0000001f799ab250
isr_el1        = 0x0000000000000040
cpuectlr_el1   = 0xc0007403c0543001
gicd_ispendr regs (Offsets 0x200 - 0x278)
 Offset:                        value
0000000000000200:               0x0000000000000000
0000000000000204:               0x0000000000000000
0000000000000208:               0x0000000000000000
000000000000020c:               0x0000000000000008
0000000000000210:               0x0000000010000000
0000000000000214:               0x0000000000000000
0000000000000218:               0x0000000000000000
000000000000021c:               0x0000000000000000
0000000000000220:               0x0000000000000000
0000000000000224:               0x0000000000000000
0000000000000228:               0x0000000000000000
000000000000022c:               0x0000000000000000
0000000000000230:               0x0000000000000000
0000000000000234:               0x0000000000000000
0000000000000238:               0x0000000080000000
000000000000023c:               0x0000000000000000
0000000000000240:               0x0000000000000000
0000000000000244:               0x0000000000000000
0000000000000248:               0x0000000000000000
000000000000024c:               0x0000000000000000
0000000000000250:               0x0000000000001800
0000000000000254:               0x0000000000000000
0000000000000258:               0x0000000000000000
000000000000025c:               0x0000000000800000
0000000000000260:               0x0000000000000000
0000000000000264:               0x0000000000000000
0000000000000268:               0x0000000000000000
000000000000026c:               0x0000000000000000
0000000000000270:               0x0000000000000000
0000000000000274:               0x0000000000000000
0000000000000278:               0x0000000000000000
000000000000027c:               0x0000000000000000

完整日志文件:

flash_debug.log (207.6 KB)

ODMDATA=“pcie@4_clk-scheme=1”

這個不需要開, 請維持原本的設定

OK,以下是修改的内容,我立刻测试,稍后给你反馈:

tegra264-bpmp-3834-0008-4071-xxxx.dts文件中:

		pcie@3 {
			//status = "disabled";	/* Modify by chenxi to support y-c8's PCIE */
			status = "okay";
...
		pcie@4 {
			//status = "disabled";	/* Modify by chenxi to support y-c8's PCIE */
			status = "okay";
...
		pcie@5 {
			//status = "okay";	/* Modify by chenxi to support y-c8's PCIE */
			status = "disabled";
...
	uphy {
		status = "okay";
		uphy0-config = <0x07>;
		//uphy1-config = <0x07>;
		uphy1-config = <0x00>;	/* Add by chenxi */

pinmux文件中:

			pex_l4_clkreq_n_pd0 {	/* Modify by chenxi to support peci c4 */
				nvidia,pins = "pex_l4_clkreq_n_pd0";
				//nvidia,function = "rsvd1";
				//nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				//nvidia,tristate = <TEGRA_PIN_ENABLE>;
				//nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,function = "pe4_clkreq_l";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
				nvidia,e-io-od = <TEGRA_PIN_ENABLE>;
				nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
			};

			pex_l4_rst_n_pd1 {
				nvidia,pins = "pex_l4_rst_n_pd1";
				//nvidia,function = "rsvd1";
				//nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				//nvidia,tristate = <TEGRA_PIN_ENABLE>;
				//nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,function = "pe4_rst_l";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
				nvidia,e-io-od = <TEGRA_PIN_ENABLE>;
				nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
			};

dtb文件中:

	bus@0 {
		/* PCIe C3 */
        pcie@a808440000 {
            status = "okay";
        };

        /* PCIe C4 */
        pcie@a808460000 {
            status = "okay";
        };

        /* PCIe C5 */
        pcie@a808480000 {
            status = "disabled";
        };

conf文件中:

source "${LDK_DIR}/t264.conf.common";

#DTB_FILE="tegra264-p4071-0000+p3834-0008-nv.dtb";
DTB_FILE="y-c8-agx-thor-382.dtb";
TBCDTB_FILE="${DTB_FILE}";
BPFDTB_FILE="tegra264-bpmp-3834-0008-4071-xxxx.dtb";
BPFFILE="bootloader/bpmp_t264-TA1090SA-A1_prod.bin";

EXTERNAL_PT_LAYOUT="tools/kernel_flash/flash_l4t_t264_nvme.xml";
EMC_BCT="tegra264-p3834-0008-sdram-bct-l4t.dts";
WB0SDRAM_BCT="tegra264-p3834-0008-sdram-bct-warmboot-l4t.dts";
BPMP_MEM_CONFIG="tegra264-p3834-0008-sdram-dfs.dts";
MISC_CONFIG="tegra264-mb1-bct-misc-p3834-xxxx-p4071-0000.dts";
SCR_CONFIG="tegra264-mb2-bct-firewall-p3834-xxxx-p4071-0000.dts";
#PINMUX_CONFIG="tegra264-mb1-bct-pinmux-p3834-xxxx-p4071-0000.dts";
PINMUX_CONFIG="tegra264-mb1-bct-pinmux-p3834-xxxx-p4071-0000-c8.dts";
PMIC_CONFIG="tegra264-mb1-bct-pmic-p3834-0008-p4071-0000.dts";
PMC_CONFIG="tegra264-mb1-bct-padvoltage-p3834-xxxx-p4071-0000.dts";
DEVICEPROD_CONFIG="tegra264-mb1-bct-cprod-p3834-xxxx-p4071-0000.dts";
PROD_CONFIG="tegra264-mb1-bct-prod-p3834-xxxx-p4071-0000.dts";
#MB2_BCT="tegra264-mb2-bct-misc-p3834-xxxx-p4071-0000.dts";
MB2_BCT="tegra264-mb2-bct-misc-p3834-xxxx-p4071-0000-c8.dts";
# Rollback protection
MINRATCHET_CONFIG="tegra264-mb1-bct-ratchet-p3834-xxxx-p4071-0000.dts";
GPIOINT_CONFIG="tegra264-mb1-bct-gpioint-p3834-xxxx-p4071-0000.dts";
#UPHY_CONFIG="tegra264-mb1-bct-uphy-lanes-p4071-0000.dts";
UPHY_CONFIG="";
RAMCODE=12;

EXTERNAL_DEVICE="nvme0n1p1";
OVERLAY_DTB_FILE="L4TConfiguration.dtbo,tegra264-p4071-0000+p3834-xxxx-dynamic.dtbo";
# Uncomment below line to enable C4 RP controller in SRIS mode
#ODMDATA="pcie@4_clk-scheme=1"
# Uncomment below line to enable C4 controller in Endpoint SRIS mode.
#ODMDATA="pcie-c4-endpoint-enable,pcie-c4-endpoint-use-int-refclk,pcie@4_clk-scheme=1_pcie-mode=2"

按照上述修改过后,flash还是无法成功,调试串口输出的日志信息如下:

[0010.937] I> MB2 finished

NOTICE:  BL31: lts-v2.8.16(release):7a2e991
NOTICE:  BL31: Built : 17:19:22, Aug 21 2025
INFO: Initializing Hafnium (SPMC)
INFO: text: 0x2039e10000 - 0x2039e39000
INFO: rodata: 0x2039e39000 - 0x2039e43000
INFO: data: 0x2039e43000 - 0x203a4b1000
INFO: stacks: 0x203a4c0000 - 0x203a4f8000
INFO: Supported bits in physical address: 48
INFO: Stage 2 has 4 page table levels with 1 pages at the root.
INFO: Stage 1 has 4 page table levels with 1 pages at the root.
INFO: Memory range:  0x80000000 - 0x800000ff
S Memory ranges:
  [80000000 - 80000100 (1 pages)]
NS Memory ranges:
WARNING: Missing NS memory ranges, default to 1TB.
INFO: Loading VM id 0x8001: optee.
INFO: Loaded with 28 vCPUs, entry at 0x203bc20000.
INFO: Loading VM id 0x8002: standalonemm.
WARNING: Memory region security state ignored for S-EL1 partitions.
WARNING: Memory region security state ignored for S-EL1 partitions.
WARNING: Memory region security state ignored for S-EL1 partitions.
INFO: Loaded with 1 vCPUs, entry at 0x203dc20000.
INFO: Hafnium initialisation completed
VM 8001: I/TC:
VM 8001: I/TC: No non-secure external DT
VM 8001: I/TC: manifest DT found
VM 8001: I/TC: Switching console to device: /ffa-console
VM 8001: I/TC: OP-TEE version: 4.4 (gcc version 13.2.0 (crosstool-NG 1.26.0)) #2 Fri Aug 22 00:24:28 UTC 2025 aarch64
VM 8001: I/TC: WARNING: This OP-TEE configuration might be insecure!
VM 8001: I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
VM 8001: I/TC: Primary CPU initializing
VM 8001: I/TC: Test TZ root key is being used. This is insecure for shipping products!
VM 8001: I/TC: Primary CPU switching to normal world boot
NOTICE: Initialized VM: 0x8001, boot_order: 0
VM 8002:   (version 38.2.0-gcid-41844464 2025-08-22T00:23:12+00:00)
VM 8002:  Boot Complete
NOTICE: Initialized VM: 0x8002, boot_order: 1
NOTICE: Finished initializing all VMs.
▒▒ERROR: camera-ip/isp5/isp5.c:2741 [isp5_pm_init] "ERROR: Failed to turn isp power on"
ERROR: camera-ip/isp5/isp5.c:2741 [isp5_pm_init] "ERROR: Failed to turn isp1 power on"
BUG: core/init/init.c:123 [init_all] "*** FIRMWARE INIT FAILED AT LEVEL 95 FEATURE ID 13 ***"
▒▒ERROR:   tegra_bpmp_ipc_init_one: BPMP firmware is not ready
ERROR:   socket 0 IVC channel init failed
ASSERT: plat/nvidia/tegra/soc/t264/plat_setup.c:716

Jetson Thor Adaptation and Bring-Up — NVIDIA Jetson Linux Developer Guide
我在Linux_for_Tegra的flash环境和Source的源码环境中都没有找到pcie-common.dtsi这个文件,请问我应该如何获取,我看日志提示BPMP firmware is not ready,开发文档中提示可以修改bpmp_fw。

Hi,

能跟你確認一下你的MGBE device tree那些有關掉嗎?

現在這個不用去debug PCIe. 你會卡在bpmp沒辦法燒純粹就是UPHY設定的問題. 跟Orin 的時候一樣.


关掉了这四个

能把你現在全部有改過的東西用附件的方式全部附上來嗎?

還有uart碰上的完整error.

你這樣一直貼圖的方式說實話很難完整確認

debug_log.txt (82.8 KB)
dtb_source.zip (1002 Bytes)
Linux_for_Tegra.zip (17.0 KB)
我修改的所有文件都在这里面了。

請問你這裡的目標有包含要打開C3嗎?

目标是打开PCIe C1,C2,C3,C4,这4个控制器。

那你的UPHY0設定沒有改到 要從7改6

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非常感谢,看起来就是uphy配置的问题,这个跟ORIN有些区别,一时没理解过来,多谢支持。

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很抱歉继续之前的帖子, 我按照同样的方法改完,C4控制器能正常工作,但是C3控制器还是无法正常工作。

请问一下,要使用C3,下述内容是必须的嘛?

ODMDATA="uphy0-config-6,pcie@3_status=okay";