Hi,
We are using Jetson AGX Xavier board as PCIe Root complex and our custom FPGA board as Endpoint. We want to set TD bit of TLP header of read request sent by Xavier i.e Root complex. How can we enable that?
Hi,
This was not enabled in rel-35 by default.
If you need it, please refer to rel-36 source code kernel/3rdparty/canonical/linux-jammy/kernel-source/drivers/pci/controller/dwc/pcie-designware.c and add static inline u32 dw_pcie_enable_ecrc(u32 val) to your rel-35 code.
Based on your answer I tried rel-36 in Jetson Orin but when i issued read request from orin, TD bit is not set. Please see below image in which read request header captured as 0x00000001 0x0000000f.
Please make sure that dw_pcie_enable_ecrc is executed in the driver code.
Also, for Orin AGX, you need to add pci=ecrc=on in kernel cmdline.
Thank you @WayneWWW . It worked Orin sent packets with TD bit set. Is it possible to set Attribute bit 0 i.e No Snoop bit in TLP header of Orin generated Packets?
Are you trying to ask this question for Orin or Xavier exactly…
This topic is in Xavier AGX forum…
I asked for Orin. Since I could easily generated TD bit in Orin, I want to set No Snoop bit along with it. Anyhow I have created new topic in Orin forum:How to enable attr[0] i.e No snoop of pcie header in AGX Orin Root Complex
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