Hi JerryChang,
OK, no problem. This is my H/W & L4T information and the steps of enabling UART7 as below:
[Information]
H/W: TX2 SOM board (P3310) + custom CA board
L4T: 32.3.1
UART7: connected with GPS
[Steps]
1.Modify the BPMP dts
a.cd /{$path}/nvidia_sdk/JetPack_4.3_Linux_P3310/Linux_for_Tegra/bootloader/t186ref
b.dtc -I dtb -O dts tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2.dtb > tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2.dts
c.Modify area as below:
serial { port = <0xff>; #port = <0x7>; has_input; };
d.dtc -I dts -O dtb tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2.dts > tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2.dtb
2.Modify the dts
a.cd /${path}/kernel/hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms
b.added area as below in tegra186-quill-common.dtsi
serial@c290000 { compatible = "nvidia,tegra186-hsuart"; iommus = <0x11 0x20>; reg = <0x0 0xc290000 0x0 0x40>; reg-shift = <0x2>; interrupts = <0x0 0x76 0x4>; nvidia,memory-clients = <0xe>; dmas = <0x25 0x2 0x25 0x2>; dma-names = "rx", "tx"; clocks = <0x10 0xd8 0x10 0x10d>; clock-names = "serial", "parent"; resets = <0x10 0x70>; reset-names = "serial"; status = "okay"; nvidia,tolerance-low-range = <0x0>; nvidia,tolerance-high-range = <0x4>; nvidia,adjust-baud-rates = <0x1c200 0x1c200 0x64>; linux,phandle = <0x194>; phandle = <0x194>; };
3.Compile the dts (ready your compile environment)
make ARCH=arm64 O=$TEGRA_KERNEL_OUT CROSS_COMPILE=${CROSS_COMPILE} -j4 dtbs
4.Flash dtb
sudo ./flash.sh -r -k kernel-dtb jetson-tx2 mmcblk0p1