how to locate pins UART5_TX J58 UART5_RX H58 ?

Yes, I mean the host PC.

I just notice your device tree does not give a status=“okay”. Is this a pure dts from jetpack?

Thank you for pointing out!
The full output is:

/proc/device-tree/serial@3140000$ xxd status
00000000: 6f6b 6179 00                             okay.
nvidia@nvidia-desktop:/proc/device-tree/serial@3140000$

And yes, it is the default image from the jetpack.
Shall I reflash the device to make sure the parameters at the host pc in the bootloader destination will match the guys in your post?

My main concern is to wire the GPS to get time synchronization somehow.
It is quite cumbersome to understand what wires to where to connect.
I have written to Garmin support inquiring them if they could provide more insights.
However, it seems like there are several frequent instructions in the internet by guys who use it with Linux workstations. Thus after wiring got sorted out it shouldn’t be an issue to set up the software component, in my opinion. However, I did not have that experience before.
I am trying to interface
http://static.garmin.com/pumac/GPS_18x_Tech_Specs.pdf

what I found at Xavier is:

cat pinmux-pins 
Pinmux settings per pin
Format: pin (name): mux_owner gpio_owner hog?
pin 0 (DAP6_SCLK_PA0): (MUX UNCLAIMED) tegra-gpio:288
pin 1 (DAP6_DOUT_PA1): (MUX UNCLAIMED) tegra-gpio:289
pin 2 (DAP6_DIN_PA2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 3 (DAP6_FS_PA3): (MUX UNCLAIMED) tegra-gpio:291
pin 4 (DAP4_SCLK_PA4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 5 (DAP4_DOUT_PA5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 6 (DAP4_DIN_PA6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 7 (DAP4_FS_PA7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 8 (CPU_PWR_REQ_0_PB0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 9 (CPU_PWR_REQ_1_PB1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 16 (QSPI0_SCK_PC0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 17 (QSPI0_CS_N_PC1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 18 (QSPI0_IO0_PC2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 19 (QSPI0_IO1_PC3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 20 (QSPI0_IO2_PC4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 21 (QSPI0_IO3_PC5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 22 (QSPI1_SCK_PC6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 23 (QSPI1_CS_N_PC7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 24 (QSPI1_IO0_PD0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 25 (QSPI1_IO1_PD1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 26 (QSPI1_IO2_PD2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 27 (QSPI1_IO3_PD3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 32 (EQOS_TXC_PE0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 33 (EQOS_TD0_PE1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 34 (EQOS_TD1_PE2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 35 (EQOS_TD2_PE3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 36 (EQOS_TD3_PE4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 37 (EQOS_TX_CTL_PE5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 38 (EQOS_RD0_PE6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 39 (EQOS_RD1_PE7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 40 (EQOS_RD2_PF0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 41 (EQOS_RD3_PF1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 42 (EQOS_RX_CTL_PF2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 43 (EQOS_RXC_PF3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 44 (EQOS_SMA_MDIO_PF4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 45 (EQOS_SMA_MDC_PF5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 48 (SOC_GPIO00_PG0): (MUX UNCLAIMED) tegra-gpio:336
pin 49 (SOC_GPIO01_PG1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 50 (SOC_GPIO02_PG2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 51 (SOC_GPIO03_PG3): (MUX UNCLAIMED) tegra-gpio:339
pin 52 (SOC_GPIO08_PG4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 53 (SOC_GPIO09_PG5): (MUX UNCLAIMED) tegra-gpio:341
pin 54 (SOC_GPIO10_PG6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 55 (SOC_GPIO11_PG7): (MUX UNCLAIMED) tegra-gpio:343
pin 56 (SOC_GPIO12_PH0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 57 (SOC_GPIO13_PH1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 58 (SOC_GPIO14_PH2): (MUX UNCLAIMED) tegra-gpio:346
pin 59 (UART4_TX_PH3): (MUX UNCLAIMED) tegra-gpio:347
pin 60 (UART4_RX_PH4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 61 (UART4_RTS_PH5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 62 (UART4_CTS_PH6): (MUX UNCLAIMED) tegra-gpio:350
pin 63 (DAP2_SCLK_PH7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 64 (DAP2_DOUT_PI0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 65 (DAP2_DIN_PI1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 66 (DAP2_FS_PI2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 67 (GEN1_I2C_SCL_PI3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 68 (GEN1_I2C_SDA_PI4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 72 (SDMMC1_CLK_PJ0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 73 (SDMMC1_CMD_PJ1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 74 (SDMMC1_DAT0_PJ2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 75 (SDMMC1_DAT1_PJ3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 76 (SDMMC1_DAT2_PJ4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 77 (SDMMC1_DAT3_PJ5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 80 (PEX_L0_CLKREQ_N_PK0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 81 (PEX_L0_RST_N_PK1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 82 (PEX_L1_CLKREQ_N_PK2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 83 (PEX_L1_RST_N_PK3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 84 (PEX_L2_CLKREQ_N_PK4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 85 (PEX_L2_RST_N_PK5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 86 (PEX_L3_CLKREQ_N_PK6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 87 (PEX_L3_RST_N_PK7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 88 (PEX_L4_CLKREQ_N_PL0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 89 (PEX_L4_RST_N_PL1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 90 (PEX_WAKE_N_PL2): (MUX UNCLAIMED) tegra-gpio:378
pin 91 (SATA_DEV_SLP_PL3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 96 (DP_AUX_CH0_HPD_PM0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 97 (DP_AUX_CH1_HPD_PM1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 98 (DP_AUX_CH2_HPD_PM2): (MUX UNCLAIMED) tegra-gpio:386
pin 99 (DP_AUX_CH3_HPD_PM3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 100 (HDMI_CEC_PM4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 101 (SOC_GPIO50_PM5): (MUX UNCLAIMED) tegra-gpio:389
pin 102 (SOC_GPIO51_PM6): (MUX UNCLAIMED) tegra-gpio:390
pin 103 (SOC_GPIO52_PM7): (MUX UNCLAIMED) tegra-gpio:391
pin 104 (SOC_GPIO53_PN0): (MUX UNCLAIMED) tegra-gpio:392
pin 105 (SOC_GPIO54_PN1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 106 (SOC_GPIO55_PN2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 112 (SDMMC3_CLK_PO0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 113 (SDMMC3_CMD_PO1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 114 (SDMMC3_DAT0_PO2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 115 (SDMMC3_DAT1_PO3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 116 (SDMMC3_DAT2_PO4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 117 (SDMMC3_DAT3_PO5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 120 (EXTPERIPH1_CLK_PP0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 121 (EXTPERIPH2_CLK_PP1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 122 (CAM_I2C_SCL_PP2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 123 (CAM_I2C_SDA_PP3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 124 (SOC_GPIO04_PP4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 125 (SOC_GPIO05_PP5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 126 (SOC_GPIO06_PP6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 127 (SOC_GPIO07_PP7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 128 (SOC_GPIO20_PQ0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 129 (SOC_GPIO21_PQ1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 130 (SOC_GPIO22_PQ2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 131 (SOC_GPIO23_PQ3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 132 (SOC_GPIO40_PQ4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 133 (SOC_GPIO41_PQ5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 134 (SOC_GPIO42_PQ6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 135 (SOC_GPIO43_PQ7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 136 (SOC_GPIO44_PR0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 137 (SOC_GPIO45_PR1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 138 (UART1_TX_PR2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 139 (UART1_RX_PR3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 140 (UART1_RTS_PR4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 141 (UART1_CTS_PR5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 144 (DAP1_SCLK_PS0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 145 (DAP1_DOUT_PS1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 146 (DAP1_DIN_PS2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 147 (DAP1_FS_PS3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 148 (AUD_MCLK_PS4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 149 (SOC_GPIO30_PS5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 150 (SOC_GPIO31_PS6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 151 (SOC_GPIO32_PS7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 152 (SOC_GPIO33_PT0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 153 (DAP3_SCLK_PT1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 154 (DAP3_DOUT_PT2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 155 (DAP3_DIN_PT3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 156 (DAP3_FS_PT4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 157 (DAP5_SCLK_PT5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 158 (DAP5_DOUT_PT6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 159 (DAP5_DIN_PT7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 160 (DAP5_FS_PU0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 168 (DIRECTDC1_CLK_PV0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 169 (DIRECTDC1_IN_PV1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 170 (DIRECTDC1_OUT0_PV2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 171 (DIRECTDC1_OUT1_PV3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 172 (DIRECTDC1_OUT2_PV4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 173 (DIRECTDC1_OUT3_PV5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 174 (DIRECTDC1_OUT4_PV6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 175 (DIRECTDC1_OUT5_PV7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 176 (DIRECTDC1_OUT6_PW0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 177 (DIRECTDC1_OUT7_PW1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 184 (GPU_PWR_REQ_PX0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 185 (CV_PWR_REQ_PX1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 186 (GP_PWM2_PX2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 187 (GP_PWM3_PX3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 188 (UART2_TX_PX4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 189 (UART2_RX_PX5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 190 (UART2_RTS_PX6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 191 (UART2_CTS_PX7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 192 (SPI3_SCK_PY0): (MUX UNCLAIMED) tegra-gpio:480
pin 193 (SPI3_MISO_PY1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 194 (SPI3_MOSI_PY2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 195 (SPI3_CS0_PY3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 196 (SPI3_CS1_PY4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 197 (UART5_TX_PY5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 198 (UART5_RX_PY6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 199 (UART5_RTS_PY7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 200 (UART5_CTS_PZ0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 201 (USB_VBUS_EN0_PZ1): (MUX UNCLAIMED) tegra-gpio:489
pin 202 (USB_VBUS_EN1_PZ2): (MUX UNCLAIMED) tegra-gpio:490
pin 203 (SPI1_SCK_PZ3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 204 (SPI1_MISO_PZ4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 205 (SPI1_MOSI_PZ5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 206 (SPI1_CS0_PZ6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 207 (SPI1_CS1_PZ7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 208 (CAN1_DOUT_PAA0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 209 (CAN1_DIN_PAA1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 210 (CAN0_DOUT_PAA2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 211 (CAN0_DIN_PAA3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 212 (CAN0_STB_PAA4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 213 (CAN0_EN_PAA5): (MUX UNCLAIMED) tegra-gpio-aon:253
pin 214 (CAN0_WAKE_PAA6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 215 (CAN0_ERR_PAA7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 216 (CAN1_STB_PBB0): tegra210-dmic.2 (GPIO UNCLAIMED) function dmic5 group can1_stb_pbb0
pin 217 (CAN1_EN_PBB1): tegra210-dmic.2 (GPIO UNCLAIMED) function dmic5 group can1_en_pbb1
pin 218 (CAN1_WAKE_PBB2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 219 (CAN1_ERR_PBB3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 224 (SPI2_SCK_PCC0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 225 (SPI2_MISO_PCC1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 226 (SPI2_MOSI_PCC2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 227 (SPI2_CS0_PCC3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 228 (TOUCH_CLK_PCC4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 229 (UART3_TX_PCC5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 230 (UART3_RX_PCC6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 231 (GEN2_I2C_SCL_PCC7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 232 (GEN2_I2C_SDA_PDD0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 233 (GEN8_I2C_SCL_PDD1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 234 (GEN8_I2C_SDA_PDD2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 240 (SAFE_STATE_PEE0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 241 (VCOMP_ALERT_PEE1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 242 (AO_RETENTION_N_PEE2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 243 (BATT_OC_PEE3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 244 (POWER_ON_PEE4): (MUX UNCLAIMED) tegra-gpio-aon:284
pin 245 (PWR_I2C_SCL_PEE5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 246 (PWR_I2C_SDA_PEE6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 248 (UFS0_REF_CLK_PFF0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 249 (UFS0_RST_PFF1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 256 (PEX_L5_CLKREQ_N_PGG0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 257 (PEX_L5_RST_N_PGG1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 258 (DIRECTDC_COMP): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 259 (SDMMC4_CLK): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 260 (SDMMC4_CMD): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 261 (SDMMC4_DQS): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 262 (SDMMC4_DAT7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 263 (SDMMC4_DAT6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 264 (SDMMC4_DAT5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 265 (SDMMC4_DAT4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 266 (SDMMC4_DAT3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 267 (SDMMC4_DAT2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 268 (SDMMC4_DAT1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 269 (SDMMC4_DAT0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 270 (SDMMC1_COMP): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 271 (SDMMC1_HV_TRIM): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 272 (SDMMC3_COMP): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 273 (SDMMC3_HV_TRIM): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 274 (EQOS_COMP): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 275 (QSPI_COMP): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 276 (SYS_RESET_N): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 277 (SHUTDOWN_N): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 278 (PMU_INT_N): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 279 (SOC_PWR_REQ): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 280 (CLK_32K_IN): (MUX UNCLAIMED) (GPIO UNCLAIMED)

That should be illustrating the actual assignment of pinmux at the Jetson device, doesn’t it?
It has in particular:

pin 138 (UART1_TX_PR2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 139 (UART1_RX_PR3): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 140 (UART1_RTS_PR4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 141 (UART1_CTS_PR5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 197 (UART5_TX_PY5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 198 (UART5_RX_PY6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 199 (UART5_RTS_PY7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 200 (UART5_CTS_PZ0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 59 (UART4_TX_PH3): (MUX UNCLAIMED) tegra-gpio:347
pin 60 (UART4_RX_PH4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 61 (UART4_RTS_PH5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 62 (UART4_CTS_PH6): (MUX UNCLAIMED) tegra-gpio:350

and I shall use of them UART5? and map it somehow to J30 pins? shall not I?

Which pin do you want to use? If you just want to use UART5 on devkit, I think it is already enabled by default. According to the first line in your jpg, it says this produce interfaces to a serial port. If UART5/UARTe is already enabled, then the problem should be in userspace now.

Thank you for following up!
Thank you for you question. That is what I am trying to determine.
Shall I procure a somewhat TTL-232R-3V3 adapter or could just wire to pins of J30 somehow?
Thank you

Sorry for my previous comments. I thought you were trying to use J58.

J58 is mapping to UART5 while J30 is the GPIO header pinout.

https://www.jetsonhacks.com/nvidia-jetson-agx-xavier-gpio-header-pinout/

Default J58 is being configured as UART pin while UART 1 on J30 is configured as GPIO pin.
It depends on what your GPS device is using. If it needs a UART serial console, just configured the pin to UART and then start to work on 232R.

BTW, I saw you ask how to enable “CONFIG_PPS_CLIENT_GPIO”. This can be added to tegra_defconfig in our kernel source (kernel-4.9/arch/arm64/config/)

Thank you for following up!
Three approaches seems determined by now:

  1. UART5 [ that will need some intrinsic connector that will allow to plug into M.2. E port and get pin-out of it to wire to]
  2. UART1 at J30 interface, [pins 8,10,11,36]
  3. TTL[usb] to serial DB9[rs232] adapter
    I will be looking into all three directions to see if at least one of them can be implemented.
    Thank you for your contribution.

Got a response from the manufacturer pertaining the integration:
I would refer you to the GPS 18x Technical Specifications document.

Section 1.6.2.1 specifies a power supply voltage between 4.0 Vdc and 5.5 Vdc. (The specs call this “Input Voltage”, but that’s intended to refer to power supply voltage.)

Section 1.6.2.3 specifies the interface requirements, but those are incorrect, as printed. The current design uses true RS-232 signaling. The original design intent was to use CMOS asynchronous serial signaling with RS-232 polarity (inverted from UART), ensuring direct compatibility with systems that had been designed for use with our older GPS 18 LVC design. Engineering “upgraded” the design to use true RS-232, but the technical documentation was not updated to reflect that fact. So, the host system should implement an RS-232 interface for connection to the GPS 18x LVC. That may occur in any manner that results in the interface to the GPS receiver being RS-232.

You cannot wire the RS-232 interface directly to a UART/GPIO port as the signaling polarities for those two interfaces are fundamentally different in that they use signaling polarities that are polar opposites. RS-232 rests low and the start bit is a low to high transition. UART rests high and the start bit is a high to low transition. Further, RS-232 uses a bipolar voltage swing (negative voltage to positive voltage) whereas UART signaling is unipolar (ground to positive voltage). While you could probably merely add signal inversion and clamping circuitry to interface between the two types of interface, the recommended solution is to add RS-232 driver circuitry between your UART/GPIO port and our GPS 18x LVC.

They seem to advise use of true RS-232, as it seems to me. Underlining that any rs232 interface will do.
Will e.g. device like : "https://www.amazon.com/St-Lab-U-224-Interface-Adapter/dp/B002P56HX2 " be an exact match of that sort?
Manufacturer responded as below to that question:
“I don’t know. I’m not sure if that thing has Linux drivers. Any RS-232 com port that is added by connection to a USB port on the computer will require drivers of some sort.”

redirect to the topic:
https://devtalk.nvidia.com/default/topic/1047944/jetson-agx-xavier/implementation-of-precise-time-synchronization-between-two-xaviers-over-wlan/

Can you explain where tegra_defconfig is located? Is there a documented procedure on how it can be updated, built and flashed to the Xavier?

@Andrey1984: were you able to sync the Xavier CPU clock to the PPS signal from the Garmin?