How to make a kernel with Dual-Diplay on R28.1

Hi Wayne,

I too am trying to get an eDP panel working on the TX1 dev kit with 28.1. I have followed your instructions here, including modifying the struct in dc.c and re-flashing the kernel. Prior to compiling the change in dc.c, I was also getting the “pclk out of range” error.

After flashing the kernel with the fix, now my system gets stuck in an endless loop during boot where neither the HDMI nor the eDP display anything. I can’t SSH into the board, and I don’t have a serial connection at the moment so I can’t grab a log. I’ll get that soon. When it’s stuck, the BL_EN pin cycles on and off at about 1Hz and my HDMI monitor flashes between a blank screen and “no signal”. It appears that it is trying to enable the display but gets stuck. I can recompile the kernel without the changes and reflash the tx1 and it boots, so I know my process is good.

I have a few more generic questions hopefully you can answer in the meantime while I get the log:

  1. Are your changes listed in “be0874.diff” intended to support an eDP panel on SOR and an HDMI monitor on SOR1 simultaneously?

  2. I am not quite sure how the LCD panel works. If I try to output a resolution that is not the panel’s native resolution, will it just not work, or will it scale up? I am trying to determine if I need to add support for my panel’s resolution in order to get this working, or if I can test with one of the built-in resolutions.

  3. Regarding your changes in the struct fb_videomode_tegra_dc_vga_mode in dc.c, how do you determine the correct clock speed and other settings to use for a given resolution?

  4. I have been able to get the BL_EN pin to function, but I have never seen any output on the BL_PWM pin. Does this pin only output a PWM signal once the screen is operational, or is this potentially a separate problem?

Thanks!
-marc

Hi marc,

This is the latest patch for this panel.

For your question:

  1. Yes, TX1 SOR has limitation that only one SOR is able to output HDMI. Thus, I use eDP on SOR0 and HDMI on SOR1.

  2. In eDP case, our board has EDID and it would be read through i2c in bootup. If you want to use own resolution, I believe it could be defined in device tree but I’ve never tried before.

  3. This vga mode is a dummy mode before we read EDID and gets the real resolution. However, somehow vga mode does not work on rel-28.1 so I move to a 480p resolution.

  4. I remembered when eDP is up, BL_EN and BL_PWM will be high. The latest patch will set this to high though GPIO.

From e3e760659a1a94d2c0bb76caf023a23783ce0440 Mon Sep 17 00:00:00 2001
Date: Mon, 25 Sep 2017 10:06:00 +0800
Subject: [PATCH] dc: auo 14" eDP bring up for k4.4 jetson

Add AUO 14" eDP driver for jetson.

Change-Id: Ibefcc9ecacaff8dd0504256332fbd947e844550e
---

diff --git a/drivers/video/tegra/dc/panel/board-panel.c b/drivers/video/tegra/dc/panel/board-panel.c
index d9e8828..9111355 100644
--- a/drivers/video/tegra/dc/panel/board-panel.c
+++ b/drivers/video/tegra/dc/panel/board-panel.c
@@ -466,8 +466,12 @@
 		break;
 	case BOARD_PM363:
 	case BOARD_E1824:
-		if (of_machine_is_compatible("nvidia,jetson-cv"))
-			is_edp_s_2160p_15_6 = true;
+		if (of_machine_is_compatible("nvidia,jetson-cv")) {
+			if (display_board.sku == 0x123)
+				is_edp_a_1080p_14_0 = true;
+			else
+				is_edp_s_2160p_15_6 = true;
+		}
 		else if (display_board.sku == 1200)
 			is_edp_i_1080p_11_6 = true;
 		else
diff --git a/drivers/video/tegra/dc/panel/panel-a-edp-1080p-14-0.c b/drivers/video/tegra/dc/panel/panel-a-edp-1080p-14-0.c
index 4dd0c69..c622eed 100644
--- a/drivers/video/tegra/dc/panel/panel-a-edp-1080p-14-0.c
+++ b/drivers/video/tegra/dc/panel/panel-a-edp-1080p-14-0.c
@@ -31,6 +31,7 @@
 static struct regulator *avdd_lcd;
 static struct regulator *vdd_ds_1v8;
 static struct regulator *avdd_3v3_dp;
+static struct regulator *avdd_io_edp;
 static u16 en_panel_rst;
 
 static int auo_edp_regulator_get(struct device *dev)
@@ -87,6 +88,13 @@
 		}
 	} else {
 		en_panel_rst = panel_of.panel_gpio[TEGRA_GPIO_RESET];
+	}
+	avdd_io_edp = regulator_get(dev, "avdd_io_edp");
+	if (IS_ERR(avdd_io_edp)) {
+		pr_err("avdd_io_edp regulator get failed\n");
+		err = PTR_ERR(avdd_io_edp);
+		avdd_io_edp = NULL;
+		goto fail;
 	}
 
 	reg_requested = true;
@@ -190,7 +198,8 @@
 {
 	int err = 0;
 
-	if (of_machine_is_compatible("nvidia,quill"))
+	if (of_machine_is_compatible("nvidia,quill") ||
+			of_machine_is_compatible("nvidia,jetson-cv"))
 		err = auo_edp_regulator_get(dev);
 	else if (of_machine_is_compatible("nvidia,ardbeg"))
 		err = ardbeg_edp_regulator_get(dev);
@@ -254,6 +263,13 @@
 		}
 	}
 	msleep(180);
+	if (avdd_io_edp) {
+		err = regulator_enable(avdd_io_edp);
+		if (err < 0) {
+			pr_err("avdd_io_edp regulator enable failed\n");
+			goto fail;
+		}
+	}
 
 	return 0;
 fail:
@@ -286,6 +302,9 @@
 	if (avdd_3v3_dp)
 		regulator_disable(avdd_3v3_dp);
 
+	if (avdd_io_edp)
+		regulator_disable(avdd_io_edp);
+
 	msleep(500);
 
 	return 0;
From d01fb093d4befc066a871e4be1000114542f6aeb Mon Sep 17 00:00:00 2001
Date: Sat, 17 Jun 2017 15:39:30 +0800
Subject: [PATCH] t210: jetson: dts: Add DTS file for AUO-14" eDP

Enable AUO-14" eDP for jetson
Add tegra210-jetson-cv-p2597-2180-a00-auo-1080p-edp.dtb

Change-Id: Ic41fd72ff545e7da714f58009c055bad29f33158
---

diff --git a/kernel-dts/Makefile b/kernel-dts/Makefile
index 6f21e65..89088fd 100644
--- a/kernel-dts/Makefile
+++ b/kernel-dts/Makefile
@@ -5,6 +5,7 @@
 dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-jetson-cv-base-p2597-2180-a00.dtb
 dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-jetson-cv-p2597-2180-a00.dtb
 dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-jetson-cv-p2597-2180-imx274-hdmi.dtb
+dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-jetson-cv-p2597-2180-a00-auo-1080p-edp.dtb
 dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-jetson-tx1-p2597-2180-a01-android-devkit.dtb
 dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-jetson-tx1-p2597-2180-a01-devkit.dtb
 dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-jetson-e-base-p2595-0000-a00.dtb
diff --git a/kernel-dts/tegra210-jetson-cv-base-p2597-2180-a00.dts b/kernel-dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
index 5b51130..ed2f890 100644
--- a/kernel-dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
+++ b/kernel-dts/tegra210-jetson-cv-base-p2597-2180-a00.dts
@@ -28,6 +28,7 @@
 #include "jetson-platforms/tegra210-jetson-cv-camera-modules.dtsi"
 #include "jetson-platforms/tegra210-pwm-fan-p2530-0930.dtsi"
 #include <panels/panel-a-wuxga-8-0.dtsi>
+#include <panels/panel-a-edp-1080p-14-0.dtsi>
 #include <panels/panel-s-edp-uhdtv-15-6.dtsi>
 #include <t210-common-platforms/tegra210-ers-hdmi-e2190-1100-a00.dtsi>
 #include <tegra210-soc/tegra210-sdhci.dtsi>
@@ -169,6 +170,9 @@
 			status = "okay";
 			pwms = <&tegra_pwm 0 40161>;
 		};
+		panel-a-edp-1080p-14-0-bl {
+			pwms = <&tegra_pwm 0 1000000>;
+		};
 		panel-s-edp-uhdtv-15-6-bl {
 			status = "okay";
 			pwms = <&tegra_pwm 0 1000000>;
@@ -278,13 +282,15 @@
 				status = "okay";
 			};
 			panel-s-edp-uhdtv-15-6 {
-				status = "okay";
 				nvidia,panel-bl-pwm-gpio = <&gpio TEGRA_GPIO(V, 0) 0>; /* PV0 */
 				nvidia,panel-rst-gpio = <&gpio TEGRA_GPIO(V, 2) 0>; /* PV2 */
 				smartdimmer {
 					status = "okay";
 				};
 			};
+			panel-a-edp-1080p-14-0 {
+				nvidia,panel-rst-gpio = <&gpio TEGRA_GPIO(V, 2) 0>; /* PV2 */
+			};
 		};
 
 		dpaux1 {
diff --git a/kernel-dts/tegra210-jetson-cv-p2597-2180-a00-auo-1080p-edp.dts b/kernel-dts/tegra210-jetson-cv-p2597-2180-a00-auo-1080p-edp.dts
new file mode 100644
index 0000000..762e097
--- /dev/null
+++ b/kernel-dts/tegra210-jetson-cv-p2597-2180-a00-auo-1080p-edp.dts
@@ -0,0 +1,80 @@
+/*
+* Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; version 2 of the License.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along
+* with this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+*
+*/
+#include "tegra210-jetson-cv-base-p2597-2180-a00.dts"
+
+/ {
+	host1x {
+		sor {
+			status = "okay";
+			panel-a-edp-1080p-14-0 {
+				status = "okay";
+			};
+			prod-settings {
+
+				prod_c_hbr {
+					prod = <
+						0x00000590 0x00f00000 0x00400000   //SOR_NV_PDISP_SOR_PLL1_0	23:20=LOADADJ	0x04 
+						>;
+				};
+				prod_c_hbr2 {
+					prod = <
+						0x00000590 0x00f00000 0x00600000   //SOR_NV_PDISP_SOR_PLL1_0	23:20=LOADADJ	0x06 
+						>;
+				};
+				prod_c_rbr {
+					prod = <
+						0x00000590 0x00f00000 0x00300000   //SOR_NV_PDISP_SOR_PLL1_0	23:20=LOADADJ	0x03
+						>;
+				};
+
+			};
+		};
+
+		dc@54200000 {
+			nvidia,dc-or-node = "/host1x/sor";
+		};
+		dpaux {
+			status = "okay";
+		};
+		dsi {
+			status = "disabled";
+			panel-a-wuxga-8-0 {
+				status = "disabled";
+			};
+		};
+	};
+
+	backlight {
+		panel-a-edp-1080p-14-0-bl {
+			status = "okay";
+		};
+		panel-a-wuxga-8-0-bl {
+			status = "disabled";
+		};
+	};
+	gpio@6000d000 {
+		lcd-bl-pwm-output-high {
+		gpio-hog;
+		output-high;
+		gpios = <
+			TEGRA_GPIO(V, 0) 0
+			>;
+		label = "lcd-bl-pwm-output-high-v0";
+		};
+	};
+};

Hi Wayne,

Thanks so much for the update. I did manage to get video on my panel for a split second. It seems to be stuck in a loop again where the panel continually flickers. I have attached the log file. Only the eDP panel is connected during this log. It seems like the Link Training fails?

The screen shows the console text and it appears to be tiled at least 3 times vertically. My panel’s native resolution is 2048 x 1536. Pic attached.

I have tried to use the serial and SSH consoles to use get-edid to learn more, but it won’t run without root privileges, and it won’t let me use sudo for some reason. I assume it’s just stuck in this loop and isn’t loading some important things.

I have hard-wired HPD to 1.8V since I have an error on my PCB that I need to fix. Would this matter?

Do you have any other recommendations? I am reviewing dp_lt.c to try to understand what’s going on, but I don’t fully understand it. Is the Link Training behavior I’m seeing normal or bad?

-marc

https://www.dropbox.com/s/r2xtsdxo6hhk2i2/IMG_7823.PNG?dl=0
log.txt (97 KB)

Hi Undertow10,

Sorry for the late reply. Do you resolve your problem?

According to topic https://devtalk.nvidia.com/default/topic/1026098, it looks resolved, right?

Could you share the solution here? Thanks.

I was finally able to get my eDP panel working after about 2 weeks thanks to Wayne’s help and reading other forum posts. After reviewing the kernel code pretty thoroughly, it appears that the driver for panel-s-edp-uhdtv-15-6 does the same thing as the AUO driver and already exists in the kernel. Rather than using the AUO DTS file that’s been mentioned here, I modified my devkit DTS file to enable the UHDTV driver:

diff --git a/kernel-dts/tegra210-jetson-tx1-p2597-2180-a01-devkit.dts b/kernel-dts/tegra210-jetson-tx1-p2597-2180-a01-devkit.dts
index 8c0fb71..4789dfb 100644
--- a/kernel-dts/tegra210-jetson-tx1-p2597-2180-a01-devkit.dts
+++ b/kernel-dts/tegra210-jetson-tx1-p2597-2180-a01-devkit.dts
@@ -28,11 +28,19 @@
 		bootloader {
 			nvidia,skip-display-init;
 		};
 	};
 
 	host1x {
 		dc@54200000 {
-			status = "disabled";
+			status = "okay";
+			nvidia,dc-or-node = "/host1x/sor";
+		};
+
+		dpaux {
+			status = "okay";
 		};
 
 		dsi {
@@ -47,10 +55,26 @@
 
 		sor {
 			panel-s-edp-uhdtv-15-6 {
-				status = "disabled";
+				status = "okay";
 			};
 			prod-settings {
-				status = "disabled";
+
+				prod_c_hbr {
+					prod = <
+						0x00000590 0x00f00000 0x00400000   //SOR_NV_PDISP_SOR_PLL1_0	23:20=LOADADJ	0x04 
+						>;
+				};
+				prod_c_hbr2 {
+					prod = <
+						0x00000590 0x00f00000 0x00600000   //SOR_NV_PDISP_SOR_PLL1_0	23:20=LOADADJ	0x06 
+						>;
+				};
+				prod_c_rbr {
+					prod = <
+						0x00000590 0x00f00000 0x00300000   //SOR_NV_PDISP_SOR_PLL1_0	23:20=LOADADJ	0x03
+						>;
+				};
+
 			};
 		};
 	};
@@ -62,25 +86,21 @@
 	};
 
 	backlight {
-		status = "disabled";
+		status = "okay";
+		power-supply = <&battery_reg>;
 		panel-a-wuxga-8-0-bl {
 			status = "disabled";
 		};
 		panel-s-edp-uhdtv-15-6-bl {
-			status = "disabled";
+			status = "okay";
+			pwms = <&tegra_pwm 0 5000000>;
 		};
 	};
 
-	sor {
-		status = "disabled";
-		prod-settings {
-			status = "disabled";
-		};
-		panel-s-edp-uhdtv-15-6 {
-			smartdimmer {
-				status = "disabled";
-			};
-		};
-	};
 };

I ran into a few hangups. First was that my panel had some EDID timing values that were not accepted by the board-panel.c code. This was resolved here by Wayne’s suggestion to modify h_ref_to_sync = 2: https://devtalk.nvidia.com/default/topic/1026098/jetson-tx1/2048x1536-edp-display-on-tx1/post/5218672/#5218672

Next, the backlight had some issues. Wayne’s DTS gpio-hog code was not working, plus hard-coding the PWM to be 100% wasn’t a good long-term solution. The BL_EN and BL_PWM pins would come on for a few seconds when first booting the kernel, but then shut down. I was able to confirm that my hardware worked using the terminal commands mentioned in this post: https://devtalk.nvidia.com/default/topic/1019016/jetson-tx1/how-to-enable-the-pwm-by-default-not-by-sysfs-control/post/5188457/#5188457

echo 0 > /sys/class/pwm/pwmchip0/export
cd /sys/class/pwm/pwmchip0/pwm0
echo 1000000 > period
echo 500000 > duty_cycle
echo 1 > enable

I traced the problem back to a log error that said “regulator_get() failed for (backlight, power)”. Even though I am not using a regulator for the backlight power (my backlight drivers run off the 19V main power), it seems the backlight code still requires a regulator to be specified. I chose a random regulator, and it magically worked. The backlight now stays on during boot, and I have full control over it from the Ubuntu GUI display brightness settings. Should I be using something else instead of this?

power-supply = <&battery_reg>;

Lastly, I had to add a board ID to configuration file: Linux_for_Tegra/bootloader/t210ref/cfg/board_config_p2597-devkit.xml

<?xml version="1.0"?>

<!-- Nvidia Tegra board info configuration file -->

<board_configs>
    <board type="proc" id="2180" sku="1000" fab="0" />
    <board type="display" id="1824" sku="0"/>
    <board type="pmu" id="2180" sku="0000" />
</board_configs>

I’m still not quite sure how this XML file works, but it appears to get read by flash.sh. The code in board-panel.c appears to try to grab these values from the DTS file under the node /chosen/display-board/, but instead the values get pulled from this XML file. Is this explained in the documentation somewhere?

The Board ID gets read by board-panel.c in a switch statement that chooses which driver to enable. The UHDTV driver gets selected if the Board ID is 1824 and you’re using a TX1. By using this Board ID, I didn’t need to modify the C code. Is the expectation that an OEM will need to append to this switch statement to support their own hardware?

The last thing I need to solve is that my system not does not default to the correct resolution on a fresh install. Once I select the correct resolution, it does persist through rebooting. I have not investigated this yet.

Hi Undertow10,

Thanks for your thorough share!
It looks like there is still bug for backlight… I’ll look for some solutions when having time.

I’m still not quite sure how this XML file works, but it appears to get read by flash.sh. The code in board-panel.c appears to try to grab these values from the DTS file under the node /chosen/display-board/, but instead the values get pulled from this XML file. Is this explained in the documentation somewhere?

AFAIK, only tx1 has this board config file because there is no plugin manager for TX1 display.

Is the expectation that an OEM will need to append to this switch statement to support their own hardware?

Yes, I believe OEM will need to append this switch logic when use DSI and eDP.

The last thing I need to solve is that my system not does not default to the correct resolution on a fresh install. Once I select the correct resolution, it does persist through rebooting. I have not investigated this yet.

Is the default resolution a 640x480 one? I have another patch in another thread that may help.
https://devtalk.nvidia.com/default/topic/1024289

Hi Wayne,

We skipped JetPack3.2, but since JetPack3.3 is going to be the last release for TX1, we are trying to get our drivers up to date. I am performing the same patches as before but the system won’t boot. The log starts to hang around [ 2.97 ] and print messages very slowly at some point during boot, and then eventually reboots due to watchdog timeout.

I tried looking at the AUO device tree example again and it seems to be similar to mine.

I have attached my patches below.

  • It seems that my "dp_c_monspecs_edid.patch" doesn't need to be applied since that was added in a recent release.
  • "edp_panel.patch" basically just bypasses the regulator requirements for the panel
  • "kernel_display.patch" was per your suggestion in JetPack3.1. Do I still need these patches for JetPack3.3?
  • -marc
    edp_panel.patch.txt (3.59 KB)
    kernel_display.patch.txt (1.23 KB)
    tegra210-jetson-tx1-p2597-2180-a01-devkit.dts.txt (1.98 KB)
    dp_c_monspecs_edid.txt (654 Bytes)
    log.txt (81 KB)

    Nevermind, it seems to work now. I’m not sure what happened, but recompiling everything at some point seems to have fixed it. I think the display was working all along, but the backlight was not. The backlight driver seems to be loaded in as a kernel module. On my working system with JetPack3.1, I could run “lsmod” and see “pwm_bl”. On my new JetPack3.3 system, it was not in the list. This was probably not getting loaded correctly because I was using some older instructions for compiling and installing kernel modules. I more closely followed the instructions in the JetPack3.3 documentation and now it works.