How to make gpio high-level in cboot?

Hi Jerry,

We need to use #define TEGRA194_AON_GPIO_PORT_BB 1 only. After making the pin num as 8. and configured as an input and tried to read the status of i/o it is working. But still as a output I am not able to toggle the i/o. I am using oscilloscope to probe the signals to check the i/o toggle.

[0124.506] I> is_gpio_valid: bank = 1, bank_Max = 5
[0125.007] I> grl_gpio_validation: Pin Read Value = 0 — Pin-16 connected to GND
[0125.007] I> is_gpio_valid: bank = 1, bank_Max = 5
[0125.507] I> grl_gpio_validation: Pin Read Value = 1 — Pin-16 connected to 3.3V

And I confirmed the respective GPIO is a part of A-ON not from MAIN GPIO Controller
gpiochip1: GPIOs 248-287, parent: platform/c2f0000.gpio, tegra-gpio-aon:
gpio-253 ( |pex-refclk-sel-low ) out lo
gpio-256 ( |sysfs ) out hi
gpio-284 ( |power-key ) in hi

And as per Wayne comment from the link “GPIO numbering - mapping to sysfs GPIO for JETSON XAVIER” Need to refer tegra194-gpio.h for xavier and tegra186-gpio.h for TX2.
Correct me If I am wrong.

After changing the pin num to 8 and as input. I am able to get the status of the i/o. But as a output. I am not able to control. And the HW is working fine. I verified from user space application.


it’s correct that you should refer to tegra194-gpio.h for Xavier’s GPIO definition.
i.e. #define TEGRA194_AON_GPIO_PORT_BB 1

you may check kernel messages for the AON-GPIO allocation range, it’s starting from 248.
i.e. [ 0.882955] gpiochip_setup_dev: registered GPIOs 248 to 287 on device: gpiochip1 (tegra-gpio-aon)

let me correct my previous comments, this pin GPIO3_PBB.00, GPIO number = 1*8+248 = 256.

Yes. Based on that kernel log messages and I derived the respective GPIO number as 256 and keeping 256 able to control the i/o in user space application and as well kernel modules.

But in case of Cboot. I need to use below formula to calculate the GPIO Pin number. Correct ?
(port*8)+pin = (1 * 8) + 0 = 8. With Pin num as 8. and GPIO as input is working. But as output not working. for using the i/o in cboot as output any other changes required. Please let us know.


hello prasanna,

since the default pin direction of GPIO3_PBB.00 is input.
you may also have MB1 configurations to update the pin direction as output.
you may review your board configuration file to have confirmation,
for example,

pinmux.0x0c303040 = 0x0000c054; # can1_stb_pbb0: rsvd0, pull-down, tristate-enable, input-enable

here’s documentation, Jetson Xavier NX and Jetson AGX Xavier Series MB1 Platform Configuration show the steps to customize the Jetson Xavier devices’ pinmux configuration file.