How to make Nano's uart work at about 8Mbps baudrate?

Autonomous Machines Jetson & Embedded Systems Jetson Nano
1

Hi

In our design, we need Nano’s UART to work at about 8Mbps baudrate. I found in the hardware design guide, the uart support up to 12Mbps, but in the header file “aarch64-linux-gnu/bits/termios.h”，the highest baudrate is 4Mbps, and the macro definitions are as follows:

#define B57600 0010001
#define B115200 0010002
#define B230400 0010003
#define B460800 0010004
#define B500000 0010005
#define B576000 0010006
#define B921600 0010007
#define B1000000 0010010
#define B1152000 0010011
#define B1500000 0010012
#define B2000000 0010013
#define B2500000 0010014
#define B3000000 0010015
#define B3500000 0010016
#define B4000000 0010017
#define __MAX_BAUD B4000000

There is a topic similar to my question, and the topic is as follws:
https://devtalk.nvidia.com/default/topic/1068997/jetson-nano/how-to-make-uart-buad-rate-work-at-about-8mbps/

But this topic did not tell how to configure device clock sources, and how to select proper divisor values for the MSB and LSB bits of the baud rate generator in the linux kernel source tree.

How to make Nano’s uart work at about 8Mbps baudrate?

Thank you!

Best regards!

2

hello wujianzhang2002,

according to Topic 1068997, please check device tree for clock sources and also adjust baud-rate settings.
thanks

3

thank you, JerryChang!

But I still don’t know how to modify the clock sources and baud-rate settings for uartc. The node for uartc in the device tree file is as follows:

uartc: serial@70006200 {
compatible = “nvidia,tegra114-hsuart”;
reg = <0x0 0x70006200 0x0 0x40>;
reg-shift = <2>;
interrupts = <0 46 0x04>;
iommus = <&smmu TEGRA_SWGROUP_PPCS>;
dmas = <&apbdma 10>, <&apbdma 10>;
dma-names = “rx”, “tx”;
clocks = <&tegra_car TEGRA210_CLK_UARTC>,
<&tegra_car TEGRA210_CLK_PLL_P>;
clock-names = “serial”, “parent”;
resets = <&tegra_car TEGRA210_CLK_UARTC>;
reset-names = “serial”;
nvidia,adjust-baud-rates = <115200 115200 100>;
status = “disabled”;
};

The node for the clock in the device tree is as follows:

tegra_car: clock {
compatible = “nvidia,tegra210-car”;
reg = <0x0 0x60006000 0x0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
status = “enabled”;
};

4

hi, JerryChang
Can you describe the configuration procedure more detail? I still don’t know how to modify the clock sources and baud-rate settings for uartc.

Thank you very much!

5

hello wujianzhang2002,

please modify these properties settings, you’ll also need to check Building the NVIDIA Kernel to compile device tree files.
once you generated customize dtb file, please refer to Flashing a Specific Partition to update device tree partitions.
thanks

6

hi, JerryChang
I kown how to build the linux kernel and the dts files, and I know how to flash the dtb to the right partition in the eMMC/SD.
The question is which properties settings need to be modified and what values should be configured, thank you very much!

Best regards!

7

Hi wujianzhang2002,

Can you please try with the new ioctl commands to set 8M baudrate?

Below codes can be referred.

struct termios2;
ioctl: TCGETS2, TCSETS2

flags to set and clear:
c_cflag &= ~CBAUD;
c_cflag |= BOTHER;
c_cflag |=CLOCAL;
c_ispeed = NEW_SPEED;
c_ospeed = NEW_SPEED;

However a slight deviation might be accepted with respect to hardware limitations based on supported tolerance range, clock parent and divisor.

Please let us know if you still have any issues.

Thanks & Regards,
Sandipan