How to manage the external PHY through MDIO

Autonomous Machines Jetson & Embedded Systems Jetson AGX Orin
1

Hi,

I’m using JP5.1.1(R35.3.1) on my Jetson AGX Orin on our custom board.

Now I want to manage a PHY through the MDC/MDIO of RGMII(ethernet@2310000). However, this PHY’s data lanes are not connected to RGMII port, only the MDC and MDIO lanes are connected to EQOS_MDC/MDIO(PF04/05).

Below is my device tree after modified:

ethernet@2310000 {
		status = "okay";
		nvidia,mac-addr-idx = <0>;
		phy-mode = "rgmii-id";
		phy-handle = <&phy>;
		nvidia,phy-reset-gpio = <&tegra_main_gpio TEGRA234_MAIN_GPIO(G, 5) 0>;
		fixed-link{
				speed = <1000>;
				full-duplex;
		};
		
		mdio {
			compatible = "nvidia,eqos-mdio";
			#address-cells = <1>;
			#size-cells = <0>;

			phy: phy@1 {
				reg = <1>;
				nvidia,phy-rst-pdelay-msec = <224>; /* msec */
				nvidia,phy-rst-duration-usec = <10000>; /* usec */
				interrupt-parent = <&tegra_main_gpio>;
				interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
				marvell,copper-mode;
				marvell,reg-init = <0x3 0x12 0x7fff 0x880>;
			};
		};
	};

After reboot, I can access the PHY’s register by using phytool. But, I find that the eth0(rgmii) is no longer linked up.

If I do not bind the phy to ethernet node, like:

ethernet@2310000 {
		status = "okay";
		asdf="sdf";
		nvidia,mac-addr-idx = <0>;
		phy-mode = "rgmii-id";
		/*phy-handle = <&phy>;*/
		nvidia,phy-reset-gpio = <&tegra_main_gpio TEGRA234_MAIN_GPIO(G, 5) 0>;
		fixed-link{
				speed = <1000>;
				full-duplex;
		};
		
		mdio {
			compatible = "nvidia,eqos-mdio";
			#address-cells = <1>;
			#size-cells = <0>;

			phy: phy@1 {
				reg = <1>;
				nvidia,phy-rst-pdelay-msec = <224>; /* msec */
				nvidia,phy-rst-duration-usec = <10000>; /* usec */
				interrupt-parent = <&tegra_main_gpio>;
				interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
				marvell,copper-mode;
				marvell,reg-init = <0x3 0x12 0x7fff 0x880>;
			};
		};
	};

After reboot, I cannot access the PHY’s register by using phytool. But, I find that the eth0(rgmii) is linked up normally.

Is there a way to achieve both? It really confuses me a lot.

Thanks.