Our company design our carrier board & almost finish our software porting. Now we are trying to measure the eye diagrams include LAN/PCIe/SATA interface.
For LAN, we have a PHY LAN port from TX2.
For PCIe, we have a mini-pcie slot from TX2. It’s for LTE function.
For SATA, we have a mini-pcie slot from TX2. It’s for mSATA function.
We must confirm that the above interface is no problem in signal transmission.
But after reading “Jetson_TX2_Series_Interface_Tuning_and_Compliance_Testing_Guide_App_Note…pdf” this document, we can’t follow the measuring method because we don’t have the same HW/SW tools like your document said.
We have a lot of experience measuring eye diagrams on X86 system, so we just want to know how to send test pattern from TX2 module according to different interface.
Actually we have the 2nd LAN used Intel i210 chip IC on our carrier board. From Intel i210 SPEC, it has “TEST MODE” so we can modify specific registers that we can use our tool to get this kind of signal to verify the eye diagram is OK or not.
So, we just want to know how to send the test pattern for LAN/PCIe/SATA. If we know that, we can use our measuring tool to get the signal.
Please feel free to help us to measure eye diagrams. Thank you.
Hi, the docs in DLC are what we can provide.
For ethernet, already listed the step of output test waveform in doc.
For PCIe, as said in doc: For an eye diagram only test, we are providing some guidance as follows for using oscilloscope on one end and signal generator on the other end of the PCIe link.
For SATA, it’s similar to that of PCIe.
Could we know what’s PCIe & SATA controller used in TX2 module?
You can refer to TRM for more info about this.
We have study TRM already and have a question.
Could you let me know how can it be set to the loopback state through the LTSSM mechanism?
Actually we have also study “Jetson_TX2_Series_Interface_Tuning_and_Compliance_Testing_Guide_App_Note…pdf” this document.
For PCIe eye diagrams method, it just can measure PCIe Rx eye diagram, but our company’s rule is need to measure PCIe Tx eye diagram. So until now we still don’t know how to measure PCIe Tx eye diagram and so does SATA eye diagram.
Please help suggest us how to measure PCIe & SATA Tx eye diagram.
As said in the application note:
However, for an eye diagram only test, we are providing some guidance as follows for using oscilloscope on one end and signal generator on the other end of the PCIe link.
- Detach the Parker SoC from the Jetson TX2 Series module.
- Detach the PCIe device from a board.
- Connect a differential probe at the pads of Parker SoC side on module.
- Connect a SMA for AWG at the pads of device side on PCB.
- Set up AWG and measure the eye diagram.