How to modify drive strength for SPI

[enlaihe]

Hi nvidia team:

I am using Orin SPI3 (master mode )to communicate with a MCU(slave mode ).
Orin SPI3 is 1.8 V and MCU is 3.3 V
Orin spi3 connected MCU with a levle shift.
below is the waveform . the blue waveform is orin spi clock.

the failing edge is bad. I think it’s because of the drive strength is weak.
So I want to ask how to modify the spi clk drive strength?
In TRM I only find drive strength info about QSPI.

[liyutai]

Which level shifter part in your design ?
I suggest to check your level shifter design to meet datasheet requirement.

[Trumany]

Hi, SPI tuning is not supported, customer is assumed to follow Design Guide well. Please check with level shift vendor for more info or choose another level shift.

[enlaihe]

the chip is NXS0140PW-Q100

[liyutai]

You can try to debug withNXB,
NXS used for open drain : I2C
NXB used for SPI.

[liyutai]

One more: I am not from NV team. I alway create many ticket to NV team like you.
It only my personally suggestion ~ Just for you reference.

[enlaihe]

Hi liyutai:
I will test with NXB.
thank you very much~

[enlaihe]

I have changed NXB chip,and the waveform is better now.

[liyutai]

Good news~