How to modify the Thor carrier board to use PCIe C4 for mounting an NVMe SSD

Robotics & Edge Computing Jetson Systems Jetson Thor
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Problem Description

The official Thor design connects the NVMe SSD to PCIe C5. We are designing our own carrier board and want to move the NVMe SSD to PCIe C4. The following software modifications have been made to the Nvidia SDK (R38.2.1_Jetpack7.0):

I want to know if these software modifications I made are feasible.
In addition, I would like to know if it is feasible to use PCIe C4 for the M.2 Key M interface on the custom board, instead of PCIe C5 recommended for the official carrier board.

1. EEPROM Modification

Modified the MB2 BCT file Linux_for_Tegra/bootloader/generic/BCT/tegra264-mb2-bct-common.dtsi:

  • Changed cvb_eeprom_read_size = <0x100> to cvb_eeprom_read_size = <0x0>

2. Pinmux Modification

Modified Jetson_Thor_Series_Modules_Pinmux_Template_Unitree_v1.5.xlsm.
After modification, the following configurations appear in tegra264-mb1-bct-pinmux-p3834-xxxx-p4071-0000.dtsi:

pex_l4_clkreq_n_pd0 {
    nvidia,pins = "pex_l4_clkreq_n_pd0";
    nvidia,function = "pe4_clkreq_l";
    nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    nvidia,tristate = <TEGRA_PIN_DISABLE>;
    nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
    nvidia,e-io-od = <TEGRA_PIN_ENABLE>;
    nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
};

pex_l4_rst_n_pd1 {
    nvidia,pins = "pex_l4_rst_n_pd1";
    nvidia,function = "pe4_rst_l";
    nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    nvidia,tristate = <TEGRA_PIN_DISABLE>;
    nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
    nvidia,e-io-od = <TEGRA_PIN_ENABLE>;
    nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
};

3. BPMP Device Tree Modification

Modified tegra264-bpmp-3834-0008-4071-xxxx.dts as follows:

pcie@4 {
    status = "okay";
    pcie-id = <0x04>;
    pcie-mode = <0x01>;
    max-link-speed = <0x05>;
};

pcie@5 {
    status = "disabled";
    pcie-id = <0x05>;
    pcie-mode = <0x01>;
    max-link-speed = <0x05>;
};

Compiled the modified .dts into tegra264-bpmp-3834-0008-4071-xxxx.dtb using dtc, then replaced these files in the SDK:

  • Linux_for_Tegra/bootloader/generic/tegra264-bpmp-3834-0008-4071-xxxx.dtb
  • Linux_for_Tegra/bootloader/tegra264-bpmp-3834-0008-4071-xxxx.dtb

4. Platform Device Tree Modification

Modified Linux_for_Tegra/source/hardware/nvidia/t264/nv-public/nv-platform/tegra264-p4071-0000.dtsi:

/* PCIe C4 is SNN on Jedha */
pcie@a808460000 {
    status = "okay";
};

/* PCIe C5 to enable NVME */
pcie@a808480000 {
    status = "okay";
};

5. ODMDATA Configuration Modification

In jetson-agx-thor-devkit.conf, uncommented and enabled:
ODMDATA="pcie@4_clk-scheme=1"

3

We have an example here to enable C4

Remember to add uphy1-config-0 in the ODMDATA.